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74AHC74-Q100;

74AHCT74-Q100

Dual D-type flip-flop with set and reset; positive-edge trigger

Rev. 2 — 21 April 2015

Product data sheet

1. General description

The 74AHC74-Q100; 74AHCT74-Q100 is a high-speed Si-gate CMOS device and is pin

compatible with Low-Power Schottky TTL (LSTTL). It is specified in compliance with

JEDEC standard No. 7-A.

The 74AHC74-Q100; 74AHCT74-Q100 is a dual positive-edge triggered, D-type flip-flop

with individual data inputs (D), clock inputs (CP), set inputs (SD) and reset inputs (RD). It

also has complementary outputs (Q and Q).

The set and reset are asynchronous active LOW inputs that operate independent of the

clock input. Information on the data input is transferred to the Q output on the LOW to

HIGH transition of the clock pulse. The data inputs must be stable one set-up time prior to

the LOW to HIGH clock transition for predictable operation.

Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock

rise and fall times.

This product has been qualified to the Automotive Electronics Council (AEC) standard

Q100 (Grade 1) and is suitable for use in automotive applications.

2. Features and benefits



Automotive product qualification in accordance with AEC-Q100 (Grade 1)



Specified from

40 C

to +85

C

and from

40 C

to +125

C



Balanced propagation delays



All inputs have Schmitt-trigger actions



Inputs accept voltages higher than V



Input levels:



For 74AHC74-Q100: CMOS level



For 74AHCT74-Q100: TTL level



ESD protection:



MIL-STD-883, method 3015 exceeds 2000 V



HBM JESD22-A114F exceeds 2000 V



MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0

)



Multiple package options

Nexperia

74AHC74-Q100; 74AHCT74-Q100

Dual D-type flip-flop with set and reset; positive-edge trigger

3. Ordering information

Table 1.

Ordering information

Package

Temperature range Name

74AHC74-Q100

74AHC74D-Q100

74AHC74PW-Q100

74AHC74BQ-Q100

40 C

to +125

C

40 C

to +125

C

40 C

to +125

C

SO14

TSSOP14

plastic small outline package; 14 leads; body width SOT108-1

3.9 mm

plastic thin shrink small outline package; 14 leads;

body width 4.4 mm

SOT402-1

Description

Version

Type number

DHVQFN14 plastic dual in-line compatible thermal enhanced

SOT762-1

very thin quad flat package; no leads; 14 terminals;

body 2.5



0.85 mm

SO14

TSSOP14

plastic small outline package; 14 leads; body width SOT108-1

3.9 mm

plastic thin shrink small outline package; 14 leads;

body width 4.4 mm

SOT402-1

74AHCT74-Q100

74AHCT74D-Q100

40 C

to +125

C

74AHCT74PW-Q100

40 C

to +125

C

74AHCT74BQ-Q100

40 C

to +125

C

DHVQFN14 plastic dual in-line compatible thermal enhanced

SOT762-1

very thin quad flat package; no leads; 14 terminals;

body 2.5



0.85 mm

4. Functional diagram

4 10

1SD 2SD

1CP

2CP

1RD 2RD

1 13

mna418

Fig 1.

Functional diagram

74AHC_AHCT74_Q100

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 2 — 21 April 2015

2 of 19

Nexperia

74AHC74-Q100; 74AHCT74-Q100

Dual D-type flip-flop with set and reset; positive-edge trigger

1SD

2CP

1CP

1RD

2SD

mna419

2RD

mna420

Fig 2.

Logic symbol

Fig 3.

IEC logic symbol

mna421

Fig 4.

Logic diagram (one flip-flop)

74AHC_AHCT74_Q100

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 2 — 21 April 2015

3 of 19

Nexperia

74AHC74-Q100; 74AHCT74-Q100

Dual D-type flip-flop with set and reset; positive-edge trigger

5. Pinning information

5.1 Pinning

(1) This is not a supply pin. The substrate is attached to this

pad using conductive die attach material. There is no

electrical or mechanical requirement to solder this pad.

However, if it is soldered, the solder land should remain

floating or be connected to GND.

Fig 5.

Pin configuration SO14 and TSSOP14

Fig 6.

Pin configuration DHVQFN14

5.2 Pin description

Table 2.

Symbol

1RD

1CP

1SD

GND

2SD

2CP

2RD

Pin description

Description

asynchronous reset direct input (active LOW)

data input

clock input (LOW to HIGH, edge-triggered)

asynchronous set direct input (active LOW)

true flip-flop output

complement flip-flop output

ground (0 V)

complement flip-flop output

true flip-flop output

asynchronous set direct input (active LOW)

clock input (LOW to HIGH, edge-triggered)

data input

asynchronous reset direct input (active LOW)

supply voltage

74AHC_AHCT74_Q100

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 2 — 21 April 2015

4 of 19

Nexperia

74AHC74-Q100; 74AHCT74-Q100

Dual D-type flip-flop with set and reset; positive-edge trigger

6. Functional description

Table 3.

Control

nSD

[1]

Function table

[1]

Input

nRD

nCP



Output

n+1

H = HIGH voltage level;

L = LOW voltage level;



= LOW to HIGH transition;

n+1

= state after the next LOW to HIGH CP transition;

X = don’t care.

7. Limiting values

Table 4.

Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol

GND

stg

tot

[1]

[2]

Parameter

supply voltage

input voltage

input clamping current

output clamping current

output current

supply current

ground current

storage temperature

total power dissipation

Conditions

Min

0.5

Max

+7.0

+20

+25

+75

+150

500

Unit

C

0.5

V or V

> V

+ 0.5 V

= l to (V

+ 0.5 V)

[1]

20

25

75

65

amb

40 C

to +125

C

[2]

The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

For SO14 packages: above 70

C

the value of P

tot

derates linearly at 8 mW/K.

For TSSOP14 packages: above 60

C

the value of P

tot

derates linearly at 5.5 mW/K.

For DHVQFN14 packages: above 60

C

the value of P

tot

derates linearly at 4.5 mW/K.

74AHC_AHCT74_Q100

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 2 — 21 April 2015

5 of 19