TJF1051
High-speed CAN transceiver
Rev. 3 — 8 February 2013
Product data sheet
1. General description
The TJF1051 is a high-speed CAN transceiver that provides an interface between a
Controller Area Network (CAN) protocol controller and the physical two-wire CAN bus.
The transceiver is designed for high-speed (up to 1 Mbit/s) CAN industrial applications,
providing differential transmit and receive capability to (a microcontroller with) a CAN
protocol controller.
The TJF1051 belongs to the third generation of high-speed CAN transceivers from NXP
Semiconductors, offering significant improvements over first- and second-generation
devices such as the TJA1050. It offers improved ElectroMagnetic Compatibility (EMC)
and ElectroStatic Discharge (ESD) performance, and also features ideal passive behavior
to the CAN bus when the supply voltage is off.
The TJF1051T/3 can be interfaced directly to microcontrollers with supply voltages from
3 V to 5 V
These features make the TJF1051 an excellent choice for all types of HS-CAN networks,
in nodes that do not require a standby mode with wake-up capability via the bus.
2. Features and benefits
2.1 General
Fully ISO 11898-2 compliant
Low ElectroMagnetic Emission (EME) and high ElectroMagnetic Immunity (EMI)
V
IO
input on the TJF1051T/3 allows for direct interfacing with 3 V to 5 V
microcontrollers
2.2 Low-power management
Functional behavior predictable under all supply conditions
Transceiver disengages from the bus when not powered up (zero load)
2.3 Protection
High ESD handling capability on the bus pins
Transmit Data (TXD) dominant time-out function
Undervoltage detection on pins V
CC
and V
IO
Thermally protected
NXP Semiconductors
TJF1051
High-speed CAN transceiver
3. Quick reference data
Table 1.
Symbol
V
CC
V
uvd(VCC)
I
CC
Quick reference data
Parameter
supply voltage
undervoltage detection voltage
on pin V
CC
supply current
Silent mode
Normal mode; bus recessive
Normal mode; bus dominant
V
ESD
V
CANH
V
CANL
electrostatic discharge voltage
voltage on pin CANH
voltage on pin CANL
HBM on pins CANH and CANL
no time limit; DC limiting value
no time limit; DC limiting value
Conditions
Min
4.5
3.5
0.1
2.5
20
8
58
58
Typ
-
-
1
5
50
-
-
-
Max
5.5
4.5
2.5
10
70
+8
+58
+58
Unit
V
V
mA
mA
mA
kV
V
V
4. Ordering information
Table 2.
Ordering information
Package
Name
TJF1051T
TJF1051T/3
[1]
[1]
Type number
Description
plastic small outline package; 8 leads; body width 3.9 mm
plastic small outline package; 8 leads; body width 3.9 mm
Version
SOT96-1
SOT96-1
SO8
SO8
TJF1051T/3 with V
IO
pin.
TJF1051
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 8 February 2013
2 of 17
NXP Semiconductors
TJF1051
High-speed CAN transceiver
5. Block diagram
V
IO(1)
5
V
CC
3
V
CC
TJF1051
TEMPERATURE
PROTECTION
V
IO(1)
SLOPE
CONTROL
AND
DRIVER
7
CANH
TXD
1
TIME-OUT
6
CANL
S
8
MODE
CONTROL
RXD
4
DRIVER
2
GND
015aaa099
(1) In the TJF1051T, the V
IO
input is connected internally to V
CC
.
Fig 1.
Block diagram
TJF1051
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 8 February 2013
3 of 17
NXP Semiconductors
TJF1051
High-speed CAN transceiver
6. Pinning information
6.1 Pinning
TXD
GND
V
CC
RXD
1
2
3
4
015aaa395
8
S
CANH
CANL
n.c.
TXD
GND
V
CC
RXD
1
2
3
4
015aaa100
8
S
CANH
CANL
V
IO
TJF1051T
7
6
5
TJF1051T/3
7
6
5
a. TJF1051T
Fig 2.
Pin configuration diagrams
b. TJF1051T/3
6.2 Pin description
Table 3.
Symbol
TXD
GND
V
CC
RXD
n.c.
V
IO
CANL
CANH
S
Pin description
Pin
1
2
3
4
5
5
6
7
8
Description
transmit data input
ground
supply voltage
receive data output; reads out data from the bus lines
not connected; in TJF1051T
supply voltage for I/O level adapter; TJF1051T/3 only
LOW-level CAN bus line
HIGH-level CAN bus line
Silent mode control input
TJF1051
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 8 February 2013
4 of 17
NXP Semiconductors
TJF1051
High-speed CAN transceiver
7. Functional description
The TJF1051 is a stand-alone high-speed CAN transceiver with Silent mode. It combines
the functionality of the TJA1050 transceiver with improved EMC and ESD handling
capability. Improved slope control and high DC handling capability on the bus pins
provides additional application flexibility. The TJF1051T/3 allows for direct interfacing to
microcontrollers with supply voltages down to 3 V.
7.1 Operating modes
The TJF1051 supports two operating modes, Normal and Silent. The operating mode is
selected via pin S. See
Table 4
for a description of the operating modes under normal
supply conditions.
Table 4.
Mode
Normal
Silent
[1]
[2]
Operating modes
Inputs
Pin S
LOW
LOW
HIGH
Pin TXD
LOW
HIGH
X
[2]
Outputs
CAN driver
dominant
recessive
recessive
Pin RXD
active
[1]
active
[1]
active
[1]
LOW if the CAN bus is dominant, HIGH if the CAN bus is recessive.
X = don't care.
7.1.1 Normal mode
A LOW level on pin S selects Normal mode. In this mode, the transceiver is able to
transmit and receive data via bus lines CANH and CANL (see
Figure 1
for the block
diagram). The differential receiver converts the analog data on the bus lines into digital
data which is output to pin RXD. The slope of the output signals on the bus lines is
controlled and optimized in a way that guarantees the lowest possible EME levels.
7.1.2 Silent mode
A HIGH level on pin S selects Silent mode. In Silent mode the transmitter is disabled,
releasing the bus pins to recessive state. All other IC functions, including the receiver,
continue to operate as in Normal mode. Silent mode can be used to prevent a faulty CAN
controller from disrupting all network communications.
7.2 Fail-safe features
7.2.1 TXD dominant time-out function
A ‘TXD dominant time-out’ timer is started when pin TXD is set LOW. If the LOW state on
pin TXD persists for longer than t
to(dom)TXD
, the transmitter is disabled, releasing the bus
lines to recessive state. This function prevents a hardware and/or software application
failure from driving the bus lines to a permanent dominant state (blocking all network
communications). The TXD dominant time-out timer is reset when pin TXD is set HIGH.
The TXD dominant time-out time also defines the minimum possible bit rate of 40 kbit/s.
7.2.2 Internal biasing of TXD and S input pins
Pin TXD has an internal pull-up to V
IO
and pin S has an internal pull-down to GND. This
ensures a safe, defined state in case one (or both) of these pins is left floating.
TJF1051
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 8 February 2013
5 of 17
