PCA8561
Automotive 18 × 4 LCD segment driver
Rev. 4 — 27 March 2015
Product data sheet
1. General description
PCA8561 is an ultra low-power LCD segment driver with 4 backplane- and 18
segment-driver outputs, with either an I
2
C- or an SPI-bus interface. It comprises an
internal oscillator, bias generation, instruction decoding, and display controller.
For a selection of NXP LCD segment drivers, see
Table 24 on page 45.
2. Features and benefits
AEC-Q100 grade 2 (up to 105
C)
compliant for automotive applications
Single chip LCD controller and driver
Selectable backplane drive configuration: static, 2, 3, or 4 backplane multiplexing
Selectable display bias configuration: static,
1
⁄
2
, or
1
⁄
3
Internal LCD bias generation with buffers
18 segment drives:
Up to 9 7-segment numeric characters
Up to 4 14-segment alphanumeric characters
Any graphics of up to 72 segments/elements
Auto-incrementing display data and instruction loading
Versatile blinking modes
Independent supplies of V
LCD
and V
DD
Power supply ranges:
1.8 V to 5.5 V for V
LCD
1.8 V to 5.5 V for V
DD
Ultra low-power consumption
400 kHz I
2
C-bus interface (PCA8561AHN)
5 MHz SPI-bus interface (PCA8561BHN)
Internally generated or externally supplied clock signal
Tiny package: HVQFN32, 5 mm
5 mm
3. Applications
Small displays integrated
in a car instrument cluster
in a control knob
Battery operated applications
Healthcare devices
NXP Semiconductors
PCA8561
Automotive 18 × 4 LCD segment driver
4. Ordering information
Table 1.
Ordering information
Package
Name
PCA8561AHN
HVQFN32
Description
Version
plastic thermal enhanced very thin quad SOT617-3
flat package; no leads;32 terminals; body
5 x 5
0.85 mm
plastic thermal enhanced very thin quad SOT617-3
flat package; no leads;32 terminals; body
5 x 5
0.85 mm
Type number
PCA8561BHN
HVQFN32
4.1 Ordering options
Table 2.
Ordering options
Orderable part
number
PCA8561AHN/AY
PCA8561BHN/AY
Sales item
(12NC)
935304072518
935305329518
Interface
type
I
2
C-bus
SPI-bus
Delivery form
tape and reel, 13 inch,
dry pack
tape and reel, 13 inch,
dry pack
IC
revision
1
1
Product type
number
PCA8561AHN/A
PCA8561BHN/A
5. Marking
Table 3.
Marking codes
Marking code
8561A
8561B
Type number
PCA8561AHN/A
PCA8561BHN/A
PCA8561
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 4 — 27 March 2015
2 of 55
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Product data sheet
Rev. 4 — 27 March 2015
3 of 55
PCA8561
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
NXP Semiconductors
6. Block diagram
Automotive 18 × 4 LCD segment driver
PCA8561
Fig 1.
Block diagram of PCA8561A
Fig 2.
Block diagram of PCA8561B
NXP Semiconductors
PCA8561
Automotive 18 × 4 LCD segment driver
7. Pinning information
7.1 Pinning
For mechanical details, see
Figure 30.
Fig 3.
Pin configuration of PCA8561AHN (HVQFN32)
For mechanical details, see
Figure 30.
Fig 4.
PCA8561
Pin configuration of PCA8561BHN (HVQFN32)
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 4 — 27 March 2015
4 of 55
NXP Semiconductors
PCA8561
Automotive 18 × 4 LCD segment driver
7.2 Pin description
Table 4.
Pin description
Input or input/output pins must always be at a defined level (V
SS
or V
DD
) unless otherwise specified.
Pin
1
2
3
4
5
7
8
10
Symbol
COM3
VLCD
VDD
VSS
[1]
RST
CLK
SCL
PORE
[2]
Type
output
supply
supply
supply
input
input/output
input
input
Description
LCD backplane output
LCD supply voltage
supply voltage
ground supply
reset input, active LOW
internal oscillator output, external oscillator input
•
must be left open if unused
serial clock input
Power-On Reset (POR) enable
•
•
12 to 29 SEG0 to SEG17
30 to 32 COM0 to COM2
PCA8561AHN PCA8561BHN
(SPI-bus)
(I
2
C-bus)
6
A0
[2]
-
input
output
output
connect to V
DD
for enabling POR
connect to V
SS
(or leave open) for disabling POR
LCD segment outputs
LCD backplane outputs
Pin layout depending on product and bus type
hardware device address selection;
•
•
-
9
11
SDA
-
A1
[2]
SDIO
-
CE
-
input/output
output
input
input
connect to V
SS
(or leave open) for logic 0
connect to V
DD
for logic 1
serial data input/output
serial data output
chip enable input, active LOW
hardware device address selection;
•
•
-
[1]
[2]
connect to V
SS
(or leave open) for logic 0
connect to V
DD
for logic 1
n.c.
-
not connected
The die paddle (exposed pad) is connected to V
SS
and should be electrically isolated.
A series resistance between V
DD
and the pin must not exceed 1 k to ensure proper functionality, see
Section 16.3.
PCA8561
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 4 — 27 March 2015
5 of 55
微控制器 MCU
