NXP Semiconductors
Advance Information
Document Number: MC34VR500
Rev. 9.0, 1/2019
Multi-output DC/DC regulator for
QorIQ LS1/T1 family of
communications processors
The 34VR500 is a high performance, highly integrated, multi-output,
SMARTMOS, DC/DC regulator solution, with integrated power MOSFETs
ideally suited for the LS1/T1 family of communication processors. Integrating
four switching and five linear regulators, the 34VR500 provides power to the
complete system, including the processor, DDR memory, and system
peripherals.
Features:
• Four buck converters:
• SW1: 4.5 A
• SW2: 2.0 A
• SW3: 2.5 A
• SW4: 1.0 A, (VTT tracking regulator)
• Five general purpose linear regulators
• DDR termination reference voltage (DDR3L and DDR4)
• Programmable low-power modes
• I
2
C control of all the regulators
• Power Control Logic with processor interface and event detection
• Auto qualified AEC Q100 grade 2
34VR500
Power Management
ES SUFFIX (WF-TYPE)
98ASA00589D
56 QFN-EP WF8X8
Applications:
• Internet of things (IoT) gateway
• Mobile wireless router
• MFP printer
• Network attached storage
• Automatic teller machine
VR500
SW1
SW2
LDO2
LDO4
LDO5
SW3
SW4
REFOUT
LDO1
LDO3
POWER CONTROL LOGIC
LS102X
VDD
TA_BB_VDD
VDDC
OVDD1/2
L1VDD
OVDD
GVDD
DDR3
VTT
HDMI
Ethernet
3.3 V
IN
BUS
Figure 1. 34VR500 simplified application diagram
* This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
© NXP B.V. 2019.
Table of Contents
1
2
3
Orderable parts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Internal block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.1 Pinout diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.2 Pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
General product characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.2 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.2 Functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Functional block requirements and behaviors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.1 Start-up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.2 16 MHz and 32 kHz clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.3 Bias and references block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.4 Power generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.5 Control interface I2C block description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Typical applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
7.2 Bill of materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
7.3 34VR500 layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
7.4 Thermal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
8.1 Packaging dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
4
5
6
7
8
9
34VR500
2
NXP Semiconductors
ORDERABLE PARTS
1
Orderable parts
This section describes the part numbers available to be purchased along with their differences. Valid orderable part numbers are provided
on the web. To determine the orderable part numbers for this device, go to
http://www.nxp.com
and perform a part number search for the
following device numbers.
Table 1. Orderable part variations
Part number
Temperature
(T
A
)
Package
SW4 VTT mode
Processor
Reference design
LS1021A IOT
Gateway
TWR-LS1021A
DDR memory
Notes
MC34VR500V1ES
MC34VR500V2ES
MC34VR500V3ES
MC34VR500V4ES
MC34VR500V5ES
MC34VR500V6ES
MC34VR500V7ES
MC34VR500V8ES
MC34VR500V9ES
MC34VR500VAES
MC34VR500VBES
Notes
1.
For tape and reel, add an R2 suffix to the part number.
2.
See
Table 8
for the start-up configuration.
-40 °C to +105 °C 56 QFN 8x8 mm
Enabled
LS1020/21/22A
Disabled
Enabled
Enabled
Enabled
Enabled
Enabled
Disabled
Disabled
Enabled
Disabled
LS1043/23A
T1023/13
LS1024A
LS1020/21/22A
LS1046A
LS1028
LS1043/23A
T1023/13
LX2160
DDR3L (VTT = 0.675 V)
N/A
LS1043ARDB
T1023RDB
DDR4 (VTT = 0.6 V)
DDR3L (VTT = 0.675 V)
(1)(2)
DDR4 (VTT = 0.6 V)
LS1046ARDB-PA
LS1028A-RDB
LS1043ARDB
T1023RDB
DDR4 (VTT = 0.6 V)
N/A
34VR500
NXP Semiconductors
3
INTERNAL BLOCK DIAGRAM
2
Internal block diagram
VR500
VLDOIN1
LDO1
LDO1
250 mA
LDO2
100 mA
LDO3
350 mA
LDO4
100 mA
LDO5
200 mA
Buck
Regulator
Reference
Generation
SW1 Buck
Regulator
4500 mA
FB1
PVIN1
LX1
LDO2
VLDOIN23
LDO3
SW2 Buck
Regulator
2000 mA
FB2
PVIN2
LX2
LDO4
VLDOIN45
LDO5
SW3 Buck
Regulator
2500 mA
FB3
PVIN3
LX3
LDO
Reference
Generation
SW4 Buck
Regulator
1000 mA
FB4
PVIN4
LX4
EPAD
VBG
VBIAS
VCCI2C
SCL
SDA
Main and Standby
Bandgap
I
2
C Interface
Main State Machine
Clocks and
Resets
REFOUT
REFIN
VHALF
VDIG
VCC
SGND4
VDIG Regulator
(Internal Use
Only)
VCC Regulator
(Internal Use
Only)
Figure 2. 34VR500 simplified internal block diagram
34VR500
4
ICTEST2
INTB
VIN
ICTEST1
EN
STBY
PORB
NXP Semiconductors
PIN CONNECTIONS
3
3.1
Pin connections
Pinout diagram
ICTEST2
VCCI2C
SGND4
56
55
54
53
52
51
50
49
48
47
46
45
44
VBIAS
43
42
DNC
41
LDO5
40
VLDOIN45
39
LDO4
38
FB3
37
PVIN3
36
LX3
35
LX3
34
PVIN3
33
DNC
32
SGND3
31
REFOUT
30
REFIN
29
VHALF
28
VDIG
DNC
DNC
26
INTB
DNC
PORB
STBY
ICTEST1
DNC
PVIN1
LX1
LX1
1
2
3
4
5
6
7
8
9
EP
PVIN1
10
LX1
11
PVIN1
12
FB1
13
SGND1
14
15
16
17
18
19
20
21
22
23
24
25
27
DNC
VLDOIN1
SGND2
FB4
PVIN4
DNC
VLDOIN23
VBG
VCC
SDA
SCL
VIN
EN
LDO1
PVIN2
PVIN2
Figure 3. 34VR500 pinout diagram
3.2
Pin definitions
Table 2. 34VR500 Pin Definitions
Pin number
1
2, 6, 16, 33,
42, 44, 45, 46
3
4
5
Pin name
INTB
DNC
PORB
STBY
ICTEST1
Pin
function
O
—
O
I
I
Max. rating
3.6 V
—
3.6 V
3.6 V
7.5 V
Type
Digital
Reserved
Digital
Digital
Digital/
Analog
Definition
Open drain interrupt signal to processor
Leave floating
Open drain reset output to processor.
Standby input signal from processor
Reserved pin. Connect to GND in application.
LDO2
LDO3
LX4
FB2
LX2
34VR500
NXP Semiconductors
5
