NXP Semiconductors
Data Sheet: Technical Data
Document Number LS1046A
Rev. 1, 03/2018
QorIQ LS1046A, LS1026A
Data Sheet
Features
• LS1046A has four cores and LS1026A has two cores
• Four 32-bit/64-bit Arm® Cortex®-v8 A72 CPUs
– Arranged as a single cluster of four cores sharing a
single 2 MB L2 cache
– Up to 1.8 GHz operation
– Single-threaded cores with 32 KB L1 data cache and
48 KB L1 instruction cache
• Hierarchical interconnect fabric
– Up to 700 MHz operation
• One 32-bit/64-bit DDR4 SDRAM memory controller
with ECC and interleaving support
– Up to 2.1 GT/s
• Data Path Acceleration Architecture (DPAA)
incorporating acceleration for the following functions:
– Packet parsing, classification, and distribution
(FMan)
– Queue management for scheduling, packet
sequencing, and congestion management (QMan)
– Hardware buffer management for buffer allocation
and de-allocation (BMan)
– Cryptography acceleration (SEC)
– IEEE 1588™ support
• Two RGMII interfaces
• Eight SerDes lanes for high-speed peripheral interfaces
– Three PCI Express 3.0 controllers
– One Serial ATA (SATA 6 Gbit/s) controller
– Up to two XFI (10 GbE) interfaces
– Up to five SGMII interfaces supporting 1000 Mbps
– Up to three SGMII interfaces supporting 2500 Mbps
– Up to one QSGMII interface
– Supports 10GBase-KR
– Supports 1000Base-KX
LS1046A
• Additional peripheral interfaces
– One Quad Serial Peripheral Interface (QSPI)
controller
– One Serial Peripheral Interface (SPI) controller
– Integrated flash controller (IFC) supporting NAND
and NOR flash
– Three high-speed USB 3.0 controllers with
integrated PHY
– One Enhanced Secure Digital Host Controller
supporting SD 3.0, eMMC 4.4, and eMMC 4.5
– Four I2C controllers
– Two 16550-compliant DUARTs and six low-power
UARTs (LPUARTs)
– General purpose IO (GPIO), eight Flextimers
– One Queue Direct Memory Access Controller
(qDMA)
– One Enhanced Direct Memory Access Controller
(eDMA)
– Global programmable interrupt controller (GIC)
– Thermal monitoring unit (TMU)
• 780 FC-PBGA package, 23 mm x 23 mm
NXP reserves the right to change the production detail specifications as may be
required to permit improvements in the design of its products.
Table of Contents
1 Introduction.......................................................................................... 3
2 Pin assignments.................................................................................... 4
2.1
2.2
780 BGA ball layout diagrams.................................................. 4
Pinout list...................................................................................10
3.18 Enhanced secure digital host controller (eSDHC).....................135
3.19 JTAG controller.........................................................................144
3.20 I2C interface.............................................................................. 147
3.21 GPIO interface...........................................................................150
3.22 GIC interface............................................................................. 153
3.23 High-speed serial interfaces (HSSI).......................................... 154
4 Security fuse processor.........................................................................180
5 Hardware design considerations...........................................................180
5.1
5.2
Clock ranges.............................................................................. 180
Minimum platform frequency requirements for high-speed
interfaces....................................................................................181
5.3
Minimum DPAA frequency requirements................................ 182
3 Electrical characteristics.......................................................................48
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
Overall DC electrical characteristics......................................... 48
Power sequencing......................................................................56
Power-down requirements.........................................................58
Power characteristics................................................................. 58
I/O power dissipation................................................................ 61
Power-on ramp rate................................................................... 64
Input clocks............................................................................... 64
RESET initialization..................................................................70
DDR4 SDRAM controller.........................................................71
6 Thermal................................................................................................ 182
6.1
6.2
6.3
Recommended thermal model...................................................184
Temperature diode.....................................................................184
Thermal management information............................................ 184
3.10 Ethernet interface, Ethernet management interface, IEEE Std
1588........................................................................................... 76
3.11 USB 3.0 interface...................................................................... 102
3.12 Integrated Flash Controller........................................................105
3.13 LPUART interface.....................................................................125
3.14 DUART interface...................................................................... 126
3.15 Flextimer interface.....................................................................128
3.16 SPI interface.............................................................................. 130
3.17 QSPI interface........................................................................... 133
7 Package information.............................................................................187
7.1
7.2
Package parameters for the FC-PBGA......................................187
Mechanical dimensions of the FC-PBGA................................. 187
8 Ordering information............................................................................189
8.1
8.2
Part numbering nomenclature....................................................189
Part marking ............................................................................. 189
9 Revision history....................................................................................190
QorIQ LS1046A, LS1026A Data Sheet, Rev. 1, 03/2018
2
NXP Semiconductors
Introduction
1 Introduction
The LS1046A is a cost-effective, power-efficient, and highly integrated system-on-chip
(SoC) design that extends the reach of the NXP value-performance line of QorIQ
communications processors. Featuring power-efficient 64-bit Arm
®
Cortex
®
-A72 cores
with ECC-protected L1 and L2 cache memories for high reliability, running up to 1.8
GHz.
The LS1046A and LS1026A processors are perfectly suited for a range of embedded
applications such as enterprise routers and switches, linecard controllers, network
attached storage, security appliances, virtual customer premise equipment (vCPE),
service providers gateways, and single board computers.
This figure shows the block diagram of the chip.
Arm® Cortex®-A72
32-bit/64-bit Core
32 KB
32 KB
32 KB
D-Cache
D-Cache
D-Cache
32 KB
D-Cache
32 KB
32 KB
48 KB
I-Cache
I-Cache
32 KB
I-Cache
I-Cache
2 MB L2 - Cache
64-bit
DDR4
Memory Controller
Secure Boot
Trust Zone
Power Management
IFC, QSPI, SPI
SD/SDIO/eMMC
DMA
2x DUART
4x I2C, GPIO
8x FlexTimer
3x USB3.0 w/PHY
Security
Queue
Engine
(SEC)
Manager
CCI-400™ Coherency Fabric
SMMUs
Frame Manager
PCIe 3.0
Parse, classify,
distribute
1G 1G
1/2.5/10G
Buffer
Manager 1G 1G
1/2.5/10G
1/2.5G
1G
SATA 3.0
PCIe 3.0
PCIe 3.0
Real Time Debug
Watchpoint
Cross
Trigger
Perf
Trace
Monitor
DPAA Hardware
4-Lane 10 GHz SerDes
4-Lane 10 GHz SerDes
6x LPUART
Core Complex
Accelerators and Memory Control
Basic Peripherals, Interconnect, and Debug
Networking Elements
Figure 1. LS1046A block diagram
QorIQ LS1046A, LS1026A Data Sheet, Rev. 1, 03/2018
NXP Semiconductors
3
Pin assignments
Arm® Cortex®-A72
32-bit/64-bit Core
32 KB
32 KB
32 KB
D-Cache
D-Cache
D-Cache
32 KB
D-Cache
32 KB
32 KB
48 KB
I-Cache
I-Cache
32 KB
I-Cache
I-Cache
2 MB L2 - Cache
64-bit
DDR4
Memory Controller
Secure Boot
Trust Zone
Power Management
IFC, QSPI, SPI
SD/SDIO/eMMC
DMA
2x DUART
4x I2C, GPIO
8x FlexTimer
3x USB3.0 w/PHY
6x LPUART
DPAA Hardware
Core Complex
Accelerators and Memory Control
Basic Peripherals, Interconnect, and Debug
Networking Elements
Buffer
Manager
1G
1G
Security
Queue
Engine
(SEC)
Manager
CCI-400™ Coherency Fabric
SMMUs
Frame Manager
SATA 3.0
PCIe 3.0
PCIe 3.0
Parse, classify,
distribute
1G
1G
1G
PCIe 3.0
Real Time Debug
Watchpoint
Cross
Trigger
Perf
Trace
Monitor
1/2.5/10G
1/2.5/10G
1/2.5G
4-Lane 10 GHz SerDes
4-Lane 10 GHz SerDes
Figure 2. LS1026A block diagram
2 Pin assignments
2.1 780 BGA ball layout diagrams
This figure shows the complete view of the LS1046A BGA ball map diagram.
Figure 4,
Figure 5, Figure 6,
and
Figure 7
show quadrant views.
QorIQ LS1046A, LS1026A Data Sheet, Rev. 1, 03/2018
4
NXP Semiconductors
Pin assignments
1
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
Y
AA
AB
AC
AD
AE
AF
AG
AH
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
A
B
C
D
E
SEE DETAIL A
SEE DETAIL B
F
G
H
J
K
L
M
N
P
R
T
U
V
W
SEE DETAIL C
SEE DETAIL D
Y
AA
AB
AC
AD
AE
AF
AG
AH
DDRC1
IFC
DUART
I2C
eSPI
eSDHC
Interrupts
Battery Backed Trust
Trust
System Control
ASLEEP
SYSCLK
DDR Clocking
RTC
Debug
DFT
JTAG
Analog Signals
Serdes 1
Serdes 2
USB3 PHY 1
USB3 PHY 2
USB PHY 3
Ethernet MI 1
Ethernet MI 2
EC1
EC2
USB
DIFF_SYSCLK
Power
Ground
No Connects
Figure 3. Complete BGA Map for the LS1046A
QorIQ LS1046A, LS1026A Data Sheet, Rev. 1, 03/2018
NXP Semiconductors
5
微控制器 MCU
