Freescale Semiconductor, Inc.
Data Sheet: Technical Data
Document Number: KL17P64M48SF2
Rev. 5, 04/2015
Kinetis KL17 Microcontroller
48 MHz ARM® Cortex®-M0+ and 32/64 KB Flash
MKL17Z32Vxx4(R)
MKL17Z64Vxx4(R)
The KL17 series is optimized for cost-sensitive and battery-
powered applications requiring low-power general purpose
connectivity. The product offers:
• Embedded ROM with boot loader for flexible program
upgrade
• High accuracy internal voltage and clock reference
• FlexIO to support any standard and customized serial
peripheral emulation
• Hardware CRC module
• Down to 46 µA/MHz in very low power run mode and 1.68
µA in stop mode (RAM + RTC retained)
64 LQFP (LH)
10x10x1.6 mm P .5
36 XFBGA (DA)
3.5x3.5x.5 mm P .5
48 & 32 QFN(FT&FM)
64 MAPBGA (MP)
7x7x.65 mm P .5(FT)
5x5x1.23 mm P .5 mm
5x5x.65 mm P .5(FM)
Core Processor
• ARM
®
Cortex
®
-M0+ core up to 48 MHz
Memories
• 32/64 KB program flash memory
• 8/16 KB SRAM
• 16 KB ROM with build-in bootloader
• 32-byte backup register
System
• 4-channel asynchronous DMA controller
• Watchdog
• Low-leakage wakeup unit
• Two-pin SWD (serial wire debug) programming and
debug interface
• Micro trace buffer
• Bit manipulation engine
• Interrupt controller
Clocks
• 48 MHz high accuracy (up to 0.5%) internal reference
clock
• 8 MHz high accuracy (up to 3%) internal reference
clock
• 1 kHz reference clock active under all low power
modes (except VLLS0)
• 32–40 kHz and 3–32 MHz crystal oscillator
Peripherals
• One UART module supporting ISO7816, operating
up to 1.5 Mbit/s
• Two low-power UART modules supporting
asynchronous operation in low-power modes
• Two I2C modules supporting up to 1 Mbit/s
• Two 16-bit SPI modules supporting up to 24 Mbit/s
for SPI1 and 12 Mbit/s for SPI0
• One FlexIO module supporting emulation of
additional UART, SPI, I2C, I2S, PWM and other
serial modules, etc.
• One 16-bit ADC module with high accurate internal
voltage reference, up to 20 channels and up to 818
ksps at equal to or less than 13-bit mode
• High-speed analog comparator containing a 6-bit
DAC for programmable reference input
Timers
• One 6-channel Timer/PWM module
• Two 2-channel Timer/PWM modules
• One low-power timer
• Periodic interrupt timer
• Real time clock
© 2014–2015 Freescale Semiconductor, Inc. All rights reserved.
Operating Characteristics
• Voltage range: 1.71 to 3.6 V
• Flash write voltage range: 1.71 to 3.6 V
• Temperature range: –40 to 105 °C
Packages
• 64 LQFP 10mm x 10mm, 0.5mm pitch, 1.6mm
thickness
• 36 XFBGA 3.5mm x 3.5mm, 0.5mm pitch, 0.5mm
thickness
• 32 QFN 5mm x 5mm, 0.5mm pitch, 0.65mm thickness
• 64 MAPBGA 5mm x 5mm, 0.5mm pitch, 1.23mm
thickness (Package Your Way)
• 48 QFN 7mm x 7mm, 0.5mm pitch, 0.65mm thickness
(Package Your Way)
Security and Integrity
• 80-bit unique identification number per chip
• Advanced flash security
• Hardware CRC module
I/O
• Up to 54 general-purpose input/output pins
Low Power
• Down to 46 µA/MHz in very low power run mode
• Down to 1.68 µA in stop mode (RAM + RTC
retained)
• Six flexible static modes
NOTE
The 48 QFN and 64 MAPBGA packages supporting MKLx7ZxxVFT4 and
MKLx7ZxxVMP4 part numbers for this product are not yet available. However, these
packages are included in Package Your Way program for Kinetis MCUs. Visit
Freescale.com/KPYW
for more details.
Related Resources
Type
Selector Guide
Product Brief
Reference
Manual
Data Sheet
Chip Errata
Package
drawing
Description
The Freescale Solution Advisor is a web-based tool that features
interactive application wizards and a dynamic product selector.
Resource
Solution Advisor
The Product Brief contains concise overview/summary information to KL1xPB
1
enable quick evaluation of a device for design suitability.
The Reference Manual contains a comprehensive description of the
structure and function (operation) of a device.
The Data Sheet includes electrical characteristics and signal
connections.
The chip mask set Errata provides additional or corrective
information for a particular device mask set.
Package dimensions are provided in package drawings.
KL17P64M48SF2RM
1
KL17P64M48SF2
1
xN87M
2
XFBGA 36-pin:
98ASA00708D
LQFP 64-pin:
98ASS23234W
QFN 32-pin:
98ASA00615D
QFN 48-pin:
98ASA00616D
MAPBGA 64-pin:
98ASA00420D
1. To find the associated resource, go to
http://www.freescale.com
and perform a search using this term.
2. To find the associated resource, go to
http://www.freescale.com
and perform a search using this term with the “x”
replaced by the revision of the device you are using.
2
Freescale Semiconductor, Inc.
Kinetis KL17 Microcontroller, Rev. 5, 04/2015
Table of Contents
1 Ordering information............................................................. 4
2 Overview............................................................................... 4
2.1 System features............................................................. 5
2.1.1
2.1.2
2.1.3
ARM Cortex-M0+ core.....................................5
NVIC................................................................ 6
AWIC............................................................... 6
4.3.7
Human-machine interfaces (HMI)....................38
4.4 KL17 Family Pinouts...................................................... 38
4.5 Package dimensions......................................................43
5 Electrical characteristics........................................................51
5.1 Ratings...........................................................................51
5.1.1
Thermal handling ratings................................. 51
5.1.2
5.1.3
5.1.4
Moisture handling ratings................................ 52
ESD handling ratings....................................... 52
Voltage and current absolute operating
ratings.............................................................. 52
2.1.4
Memory............................................................7
2.1.5
Reset and boot................................................ 7
2.1.6
Clock options................................................... 9
2.1.7
Security............................................................12
2.1.8
Power management........................................ 12
2.1.9
LLWU...............................................................14
2.1.10 Debug controller.............................................. 15
2.1.11 COP................................................................. 15
2.2 Peripheral features........................................................ 16
2.2.1
BME................................................................. 16
2.2.2
DMA and DMAMUX.........................................16
2.2.3
TPM................................................................. 17
2.2.4
ADC................................................................. 17
2.2.5
VREF............................................................... 18
2.2.6
CMP.................................................................19
2.2.7
RTC................................................................. 19
2.2.8
PIT................................................................... 20
2.2.9
2.2.10
2.2.11
2.2.12
2.2.13
2.2.14
2.2.15
LPTMR............................................................ 20
CRC................................................................. 21
UART............................................................... 21
LPUART.......................................................... 22
SPI................................................................... 22
I2C................................................................... 23
FlexIO.............................................................. 23
5.2 General.......................................................................... 53
5.2.1
AC electrical characteristics............................ 53
5.2.2
Nonswitching electrical specifications............. 53
5.2.3
Switching specifications...................................68
5.2.4
Thermal specifications..................................... 69
5.3 Peripheral operating requirements and behaviors......... 70
5.3.1
Core modules.................................................. 70
5.3.2
System modules.............................................. 72
5.3.3
Clock modules................................................. 72
5.3.4
Memories and memory interfaces................... 75
5.3.5
Security and integrity modules........................ 77
5.3.6
Analog............................................................. 77
5.4 Timers............................................................................ 85
5.5 Communication interfaces............................................. 85
5.5.1
5.5.2
5.5.3
SPI switching specifications............................ 85
Inter-Integrated Circuit Interface (I2C) timing.. 89
UART............................................................... 91
6 Design considerations...........................................................91
6.1 Hardware design considerations................................... 91
6.1.1
Printed circuit board recommendations........... 92
6.1.2
6.1.3
6.1.4
Power delivery system.....................................92
Analog design.................................................. 93
Digital design................................................... 93
2.2.16 Port control and GPIO..................................... 24
3 Memory map......................................................................... 26
4 Pinouts.................................................................................. 27
4.1 KL17 Signal Multiplexing and Pin Assignments.............27
4.2 Pin properties.................................................................30
4.3 Module Signal Description Tables................................. 33
4.3.1
4.3.2
4.3.3
4.3.4
4.3.5
4.3.6
Core modules.................................................. 33
System modules.............................................. 33
Clock modules................................................. 34
Analog............................................................. 34
Timer Modules................................................. 35
Communication interfaces............................... 36
6.1.5
Crystal oscillator.............................................. 96
6.2 Software considerations................................................ 98
7 Part identification...................................................................99
7.1 Description..................................................................... 99
7.2 Format........................................................................... 99
7.3 Fields............................................................................. 99
7.4 Example......................................................................... 100
8 Revision history.....................................................................100
Kinetis KL17 Microcontroller, Rev. 5, 04/2015
3
Freescale Semiconductor, Inc.
Ordering information
1 Ordering information
The following chips are available for ordering.
Table 1. Ordering information
Product
Part number
Marking
(Line1/Line2)
MKL17Z64VLH4
MKL17Z32VLH4
MKL17Z64VDA4
MKL17Z32VDA4
MKL17Z64VFM4
MKL17Z32VFM4
MKL17Z64VMP4
MKL17Z32VMP4
MKL17Z64VFT4
MKL17Z32VFT4
MKL17Z64 / VLH4
MKL17Z32 / VLH4
M17M6
M17M5
M17M6V
M17M5V
TBD
TBD
TBD
TBD
Memory
Flash
(KB)
64
32
64
32
64
32
64
32
64
32
SRAM
(KB)
16
8
16
8
16
8
16
8
16
8
Package
Pin
count
64
64
36
36
32
32
64
64
48
48
Package
IO and ADC channel
GPIOs
GPIOs
(INT/HD)
1
54/6
54/6
32/6
32/6
28/6
28/6
54/6
54/6
40/6
40/6
ADC
channels
(SE/DP)
20/4
20/4
15/4
15/4
11/2
11/2
20/4
20/4
18/3
18/3
LQFP
LQFP
XFBGA
XFBGA
QFN
QFN
MAPBGA
MAPBGA
QFN
QFN
54
54
32
32
28
28
54
54
40
40
1. INT: interrupt pin numbers; HD: high drive pin numbers
NOTE
The 48 QFN and 64 MAPBGA packages supporting MKLx7ZxxVFT4 and
MKLx7ZxxVMP4 part numbers for this product are not yet available.
However, these packages are included in Package Your Way program for
Kinetis MCUs. Visit Freescale.com/KPYW for more details.
2 Overview
The following figure shows the system diagram of this device
4
Freescale Semiconductor, Inc.
Kinetis KL17 Microcontroller, Rev. 5, 04/2015
Overview
GPIOA
Master
Cortex M0+
IOPORT
Debug
(SWD)
NVIC
CM0+ Core
Slave
GPIOB
GPIOC
GPIOD
GPIOE
ADC(16 bit 16ch)
M0
FMC
64 KB
Flash
CMP
1.2 V Voltage reference
TPM0(6 channel)
Crossabar Switch(Platform Clock - Max 48MHZ)
S0
16 KB ROM
TPM1(2 channel)
Peripheral Bridge(Bus Clock - Max 24MHZ)
TPM2(2 channel)
Low Power Timer
PIT
RTC
LPUART0
LPUART1
UART2
SPI0
SPI1
I2C0
I2C1
FlexIO
Watchdog(COP)
Register File(32 Bytes)
4-ch
DMA
DMA
MUX
M2
S1
16 KB RAM
S2
BME
MCG - Lite
HIRC48M
OSC
LIRC2M/8M
CRC
LLWU
RCM
SMC
PMC
Figure 1. System diagram
The crossbar switch connects bus masters and slaves using a crossbar switch structure.
This structure allows up to four bus masters to access different bus slaves
simultaneously, while providing arbitration among the bus masters when they access
the same slave.
2.1 System features
The following sections describe the high-level system features.
Kinetis KL17 Microcontroller, Rev. 5, 04/2015
5
Freescale Semiconductor, Inc.
