Freescale Semiconductor
Data Sheet: Technical Data
Document Number: MPC5645S
Rev. 13
,
04/2015
MPC5645S
Qorivva MPC5645S
Microcontroller Data Sheet
The Qorivva MPC5645S represents a new generation of
32-bit microcontrollers targeting single-chip automotive
instrument cluster applications. MPC5645S devices are part
of the MPC56xxS family of Power Architecture
®
-based
devices. This family has been designed with an emphasis on
providing cost-effective and high quality graphics capabilities
in order to satisfy the increasing market demand for color
Thin Film Transistor (TFT) displays within the vehicle
cockpit. Traditional cluster functions, such as gauge drive,
real time counter, and sound generation are also integrated on
each device.
Devices in the MPC56xxS family contain between 256 KB
and 2 MB internal flash memory. The family allows for easy
expansion and covers a broad range of cluster applications
from low to high-end enabling users to design a complete
platform around one common architecture. Serial flash
memory and DRAM interfaces are provided to allow even
greater system flexibility.
The MPC5645S is designed to reduce development and
production costs of TFT-based instrument cluster displays by
providing a single-chip solution with the processing and
storage capacity to host and execute real-time application
software and drive TFT displays directly.
The MPC5645S features a 2D OpenVG graphics accelerator,
Video Input Unit (VIU2) and two on-chip display control
units (DCU3 and DCULite) designed to drive two color TFT
displays simultaneously. The MPC5645S includes an
enhanced QuadSPI Serial Flash Controller and an optional
DRAM controller allowing graphics RAM expansion
externally.
The MPC5645S is compatible with the existing development
infrastructure of current Power Architecture devices and are
supported with software drivers, operating systems and
configuration code to assist with application development.
1
416 TEPBGA
27 mm × 27 mm
208 LQFP
28 mm × 28 mm
176 LQFP
24 mm × 24 mm
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.1 Device comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.2 Block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.3 Feature list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.4 Feature details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pinout and signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . 24
2.1 176 LQFP package pinout . . . . . . . . . . . . . . . . . . . . . . 24
2.2 208 LQFP package pinout . . . . . . . . . . . . . . . . . . . . . . 25
2.3 416 TEPBGA package pinout. . . . . . . . . . . . . . . . . . . . 26
2.4 Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
System design information. . . . . . . . . . . . . . . . . . . . . . . . . . . 59
3.1 Power-up sequencing. . . . . . . . . . . . . . . . . . . . . . . . . . 59
Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
4.1 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
4.2 Parameter classification . . . . . . . . . . . . . . . . . . . . . . . . 60
4.3 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . 60
4.4 Recommended operating conditions . . . . . . . . . . . . . . 62
4.5 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . 64
4.6 EMI (electromagnetic interference) characteristics . . . 69
4.7 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
4.8 DC electrical specifications. . . . . . . . . . . . . . . . . . . . . . 74
4.9 SSD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
4.10 RESET electrical characteristics . . . . . . . . . . . . . . . . . 84
4.11 Fast external crystal oscillator (4–16 MHz) electrical
characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
4.12 Slow external crystal oscillator (32 KHz) electrical
characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
4.13 FMPLL electrical characteristics. . . . . . . . . . . . . . . . . . 89
4.14 Fast internal RC oscillator (16 MHz) electrical
characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
4.15 Slow internal RC oscillator (128 kHz) electrical
characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
4.16 Flash memory electrical characteristics . . . . . . . . . . . . 91
4.17 ADC parameters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
4.18 AC specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
4.19 AC timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . 134
5.1 176 LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
5.2 208 LQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
5.3 416 TEPBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
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© Freescale Semiconductor, Inc., 2009
–
2015. All rights reserved.
1
1.1
Overview
Device comparison
Table 1. MPC5645S device comparison
Feature
MPC5645S
176 LQFP
208 LQFP
e200z4d
4 KB Instruction-Cache
16-entry Memory Management Unit (MMU)
Floating Point Unit (FPU)
Signal Processing Extension (SPE)
Static–125 MHz
2 MB
64 KB
1 MB
16 entry
16 channels
No
Yes (OpenVG 1.1)
Yes
No
No
Yes
Yes
4 motors
Yes
Yes
Yes
Yes
8 ch, 32-bit
Yes
4 ch, 32-bit
20 ch, 16-bit: IC / OC / OPWM
8 ch, 16-bit: IC / OC
4 ch, 16-bit: IC / OC / OPWM / QDEC
16 channels, 10-bit
20 channels, 10-bit
6 motors
Yes
Yes
Yes
416 TEPBGA
Package
CPU
Execution speed
Flash memory (ECC)
RAM (ECC)
On-chip graphics RAM (no ECC)
MPU
eDMA
DRAM controller
OpenVG Graphics Accelerator
(GFX2D)
Display Control Unit (DCU3)
Display Control Unit Lite (DCULite)
Timing Controller (TCON) and RSDS
interface
Video Input Unit (VIU2)
QuadSPI serial flash interface
Stepper Motor Controller (SMC)
Stepper Stall Detect (SSD)
Sound Generator Module (SGM)
32 kHz external crystal oscillator
Real Time Counter and Autonomous
Periodic Interrupt (RTC/API)
Periodic interrupt timer (PIT)
Software Watchdog Timer (SWT)
System Timer Module (STM)
Timed I/O
1
Analog-to-Digital Converter (ADC)
2
Qorivva MPC5645S Microcontroller Data Sheet, Rev. 13
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Freescale Semiconductor
Table 1. MPC5645S device comparison (continued)
Feature
Package
CAN (64 mailboxes)
CAN sampler
Serial communication interface
SPI
I
2
C
GPIO
Debug
1
2
3
4
MPC5645S
176 LQFP
208 LQFP
3 × FlexCAN
Yes
3 × LINFlex
2 × DSPI
4
128
150
Nexus Class 3 (4×MDO)
4
177
3
Nexus Class 3 (12×MDO)
4 × LINFlex
3 × DSPI
416 TEPBGA
IC-Input Capture, OC-Output Compare, OPWM-Output Pulse Width Modulation, QDEC- Quadrature Decode Mode
Support for external multiplexer enabling up to 8 channels
The 416-pin GPIO count does not include the DRAM interface, which is dedicated to DRAM only.
Nexus pins are multiplexed with other functional pins on 176 LQFP and 208 LQFP package options.
Qorivva MPC5645S Microcontroller Data Sheet, Rev. 13
Freescale Semiconductor
3
1.2
Block diagram
System
integration
VReg
Nexus 3+
Oscillator
FMPLL 0
FMPLL 1
eDMA
RTC/32Kosc
INTC
MMU
I-CACHE
VIU2
DCU3
Debug
JTAG
Crossbar switch masters
e200z4d
GFX2D
DCULite
TCON / RSDS
Crossbar Switch
Memory Protection Unit
PIT
STM
SWT
BAM
Flash
memory
2 MB
EEE
SRAM
64 KB
Graphics
SRAM
1 MB
PBRIDGE
QuadSPI
DRAM interface
RLE decoder
Crossbar switch slaves
Communication I/O system
FlexCAN 0
FlexCAN 1
FlexCAN 2
LINFlex 0
LINFlex 1
LINFlex 2
LINFlex 3
eMIOS 0
eMIOS 1
DSPI 0
DSPI 1
DSPI 2
SMC 0
SMC 1
SMC 2
SMC 3
SMC 4
SSD
ADC
BAM
eDMA
DCU3
DCULite
DSPI
eMIOS
FlexCAN
FMPLL
GFX2D
INTC
JTAG
MMU
QuadSPI
– Analog-to-Digital Converter
– Boot Assist Module
– Enhanced Direct Memory Access Controller
– Display Control Unit
– Display Control Unit Lite
– Serial Peripherals Interface
– Enhanced Modular Input/Output System
– Controller Area Network Controller
– Frequency-Modulated Phase-Locked Loop
– OpenVG Graphics Accelerator
– Interrupt Controller
– Joint Test Action Group interface
– Memory Management Unit
– Quad IO serial flash interface
PBRIDGE
PIT
RLE
RSDS
RTC
SGM
SMC
SSD
STM
SWT
TCON
VIU2
VReg
– Peripheral Bridge
– Periodic Interrupt Timer
– Run Length Encoding
– Reduced-Swing Differential Signal interface
– Real Time Clock
– Sound Generator Module
– Stepper Motor Controller
– Stepper Stall Detect
– System Timer Module
– Software Watchdog Timer
– Timing Controller
– Video Input Unit
– Voltage regulator
Figure 1. MPC5645S block diagram
Qorivva MPC5645S Microcontroller Data Sheet, Rev. 13
4
Freescale Semiconductor
SMC 5
I
2
C 0
I
2
C 1
I
2
C 2
I
2
C 3
SGM
ADC
1.3
•
Feature list
Dual-issue, 32-bit Power Architecture Book E compliant CPU core complex (e200z4d)
— Memory Management Unit (MMU)
— 4 KB, 2/4-way instruction cache
2 MB on-chip ECC flash memory with:
— Flash memory controller
— Prefetch buffers
64 KB on-chip ECC SRAM
1 MB on-chip non-ECC graphics SRAM with two-port graphics SRAM controller
Memory Protection Unit (MPU) with up to 16 region descriptors and 32-byte region granularity to provide basic
memory access permission and ensure separation between different codes and data
Interrupt Controller (INTC) with 163 peripheral interrupt sources and eight software interrupts
Two Frequency-Modulated Phase-Locked Loops (FMPLLs)
— Primary FMPLL (FMPLL0) provides a system clock up to 125 MHz
— Auxiliary FMPLL (FMPLL1) is available for use as an alternate, modulated or non-modulated clock source to
eMIOS modules, QuadSPI and as alternate clock to the DCU and DCU-Lite for pixel clock generation
Crossbar switch architecture enables concurrent access of peripherals, flash memory or RAM from multiple bus
masters
16-channel Enhanced Direct Memory Access controller (eDMA) with multiple transfer request sources using a DMA
channel multiplexer
Boot Assist Module (BAM) with 8 KB dedicated ROM for embedded boot code supports boot options including
download of boot code via a serial link (CAN or SCI)
Two Display Control Units (DCU3 and DCULite) for direct drive of up to two TFT LCD displays up to XGA
resolution
Timing Controller (TCON) and RSDS interface for the DCU3 module
2D OpenVG 1.1 and raster graphics accelerator (GFX2D)
Video Input Unit (VIU2) supporting 8/10-bit ITU656 video input, YUV to RGB conversion, video down-scaling,
de-interlacing, contrast adjustment and brightness adjustment.
DRAM controller supporting DDR1, DDR2, and LPDDR1 DRAMs
Stepper Motor Controller (SMC)
— High-current drivers for up to six instrument cluster gauges driven in full dual H-bridge configuration
— Stepper motor return-to-zero and stall detection module
— Stepper motor short circuit detection
Sound Generator Module (SGM)
— 4-channel mixer
— Supports PCM wave playback and synthesized tones
— Optional PWM or I
2
S outputs
Two 16-channel Enhanced Modular Input Output System (eMIOS) modules
— Support a range of 16-bit Input Capture, Output Compare, Pulse Width Modulation and Quadrature Decode
functions
10-bit Analog-to-Digital Converter (ADC) with a maximum conversion time of 1
μs
— Up to 20 internal channels
— Up to 8 external channels
Three Deserial Serial Peripheral Interface (DSPI) modules for full-duplex, synchronous, communications with
external devices
QuadSPI serial flash memory controller
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Qorivva MPC5645S Microcontroller Data Sheet, Rev. 13
Freescale Semiconductor
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