NXP Semiconductors
Data Sheet: Technical Data
Document Number MC9S08PL60
Rev. 3, 08/2019
MC9S08PL60 Series Data
Sheet
Supports: MC9S08PL60 and
MC9S08PL32
Key features
• 8-Bit S08 central processor unit (CPU)
– Up to 20 MHz bus at 2.7 V to 5.5 V across
temperature range of -40 °C to 85 °C
– Supporting up to 40 interrupt/reset sources
– Supporting up to four-level nested interrupt
– On-chip memory
– Up to 60 KB flash read/program/erase over full
operating voltage and temperature
– Up to 256 byte EEPROM; 2-byte erase sector;
program and erase while executing flash
– Up to 4096 byte random-access memory (RAM)
– Flash and RAM access protection
• Power-saving modes
– One low-power stop mode; reduced power wait
mode
– Peripheral clock enable register can disable clocks to
unused modules, reducing currents; allows clocks to
remain enabled to specific peripherals in stop3 mode
• Clocks
– Oscillator (XOSC) - loop-controlled Pierce
oscillator; crystal or ceramic resonator range of
31.25 kHz to 39.0625 kHz or 4 MHz to 20 MHz
– Internal clock source (ICS) - containing a frequency-
locked-loop (FLL) controlled by internal or external
reference; precision trimming of internal reference
allowing 1% deviation across temperature range of 0
°C to 70 °C and 2% deviation across temperature
range of -40 °C to 85 °C; up to 20 MHz
• System protection
– Watchdog with independent clock source
– Low-voltage detection with reset or interrupt;
selectable trip points
– Illegal opcode detection with reset
– Illegal address detection with reset
MC9S08PL60
• Development support
– Single-wire background debug interface
– Breakpoint capability to allow three breakpoints
setting during in-circuit debugging
– On-chip in-circuit emulator (ICE) debug module
containing two comparators and nine trigger modes
• Peripherals
– ACMP - one analog comparator with both positive
and negative inputs; separately selectable interrupt
on rising and falling comparator output; filtering
– ADC - 16-channel, 10-bit resolution; 2.5 µs
conversion time; data buffers with optional
watermark; automatic compare function; internal
bandgap reference channel; operation in stop mode;
optional hardware trigger
– CRC - programmable cyclic redundancy check
module
– FTM - three flex timer modulators modules
including one 6-channel and two 2-channel ones;
16-bit counter; each channel can be configured for
input capture, output compare, edge- or center-
aligned PWM mode
– MTIM - one modulo timers with 8-bit prescaler and
overflow interrupt
– RTC - 16-bit real timer counter (RTC)
– SCI - three serial communication interface (SCI/
UART) modules optional 13-bit break; full duplex
non-return to zero (NRZ); LIN extension support
• Input/Output
– Up to 57 GPIOs including one output-only pin
– Two 8-bit keyboard interrupt modules (KBI)
– Two true open-drain output pins
• Package options
– 64-pin QFP
– 44-pin LQFP
– 32-pin LQFP
NXP reserves the right to change the production detail specifications as may be
required to permit improvements in the design of its products.
Table of Contents
1
2
3
MCU block diagram...........................................................................3
Orderable part numbers......................................................................5
Part identification............................................................................... 5
3.1 Description.................................................................................5
3.2 Format........................................................................................5
3.3 Fields..........................................................................................6
3.4 Example..................................................................................... 6
4
5
Parameter Classification.....................................................................6
Ratings................................................................................................7
5.1 Thermal handling ratings...........................................................7
5.2 Moisture handling ratings.......................................................... 7
5.3 ESD handling ratings.................................................................7
5.4 Voltage and current operating ratings........................................8
6
General............................................................................................... 9
6.1 Nonswitching electrical specifications...................................... 9
6.1.1
6.1.2
6.1.3
DC characteristics........................................................ 9
Supply current characteristics...................................... 13
EMC performance........................................................14
9
8
7
6.2.1
6.2.2
6.2.3
Control timing..............................................................15
Debug trace timing specifications................................16
FTM module timing.....................................................17
6.3 Thermal specifications...............................................................18
6.3.1
6.3.2
Thermal operating requirements.................................. 18
Thermal characteristics................................................ 18
Peripheral operating requirements and behaviors.............................. 19
7.1 External oscillator (XOSC) and ICS characteristics..................19
7.2 NVM specifications................................................................... 21
7.3 Analog........................................................................................22
7.3.1
7.3.2
ADC characteristics..................................................... 22
Analog comparator (ACMP) electricals...................... 25
Dimensions.........................................................................................25
8.1 Obtaining package dimensions.................................................. 25
Pinout................................................................................................. 26
9.1 Signal multiplexing and pin assignments.................................. 26
9.2 Device pin assignment...............................................................28
10 Revision history................................................................................. 31
6.2 Switching specifications............................................................ 15
MC9S08PL60 Series Data Sheet, Rev. 3, 08/2019
2
NXP Semiconductors
MCU block diagram
1 MCU block diagram
The block diagram below shows the structure of the MCUs.
MC9S08PL60 Series Data Sheet, Rev. 3, 08/2019
NXP Semiconductors
3
MCU block diagram
PTA0/KBI0P0/FTM0CH0/ACMP0/ADP0
PTA1/KBI0P1/FTM0CH1/ACMP1/ADP1
PTA2/KBI0P2/RxD0
1
PTA3/KBI0P3/TxD0
1
PTA4/ACMPO/BKGD/MS
2
PTA5/IRQ/TCLK0/RESET
PTA6/ADP2
PTA7/ADP3
PTB0/KBI0P4/RxD0/ADP4
PTB1/KBI0P5/TxD0/ADP5
PTB2/KBI0P6/ADP6
PTB3/KBI0P7/ADP7
PTB4/FTM2CH4
PTB5/FTM2CH5
PTB6/XTAL
PTB7/EXTAL
PTC0/FTM2CH0/ADP8
PTC1/FTM2CH1/ADP9
PTC2/FTM2CH2/ADP10
PTC3/FTM2CH3/ADP11
PTC4/FTM1CH0/RTCO
PTC5/FTM1CH1
PTC6/RxD1
PTC7/TxD1
PTD0/KBI1P0/FTM2CH2
PTD1/KBI1P1/FTM2CH3
PTD2/KBI1P2
PTD3/KBI1P3
PTD4/KBI1P4
PTD5/KBI1P5
PTD6/KBI1P6/RxD2
PTD7/KBI1P7/TxD2
KEYBOARD INTERRUPT
CPU
BDC
MODULE (KBI0)
KBYBOARD INTERRUPT
MODULE (KBI1)
(MTIM0)
WDOG
1 kHz OSC
IRQ
LVD
2-CH FLEX TIMER
MODULE (FTM0)
INTERRUPT PRIORITY
CONTROLLER(IPC)
ON-CHIP ICE AND
DEBUG MODUE (DBG)
USER FLASH
MC9S08PL60 = 60,864 bytes
MC9S08PL32 = 32,768 bytes
USER EEPROM
MC9S08PL60 = 256 bytes
MC9S08PL32 = 256 bytes
USER RAM
MC9S08PL60 = 4,096 bytes
MC9S08PL32 = 4,096 bytes
20 MHz INTERNAL CLOCK
SOURCE (ICS)
2-CH FLEX TIMER
MODULE (FTM1)
6-CH FTM TIMER
MODULE (FTM2)
SERIAL COMMUNICATION
INTERFACE (SCI0)
INTERFACE (SCI1)
SERIAL COMMUNICATION
INTERFACE (SCI2 )
Port D
SERIAL COMMUNICATION
Port C
Port B
SYSTEM INTEGRATION
MODULE (SIM)
8-BIT MODULO TIMER
Port A
HCS08 CORE
REAL-TIME COUNTER
(RTC)
ANALOG COMPARATOR
(ACMP)
PTE0/TCLK1
PTE1
PTE2
PTE3
PTE4
PTE5
PTE6
PTE7/TCLK2
PTF0
PTF1
PTF2
PTF3
PTF4/ADP12
PTF5/ADP13
PTF6/ADP14
PTF7/ADP15
PTG0
PTG1
PTG2
PTG3
PTH0/FTM2CH0
PTH1/FTM2CH1
PTH2/BUSOUT
3
PTH6
PTH7
EXTAL
XTAL
V
DD
V
SS
V
DD
4
V
SS
4
V
SS
4
V
REFH
V
DDA
V
REFL
V
SSA
EXTERNAL OSCILLATOR
SOURCE (XOSC)
POWER MANAGEMENT
CONTROLLER (PMC)
1. PTA2 and PTA3 operate as true open drain when working as output
.
2. PTA4/ACMPO/BKGD/MS is an output-only pin when used as port pin.
3. The frequency of the clock from BUSOUT must be equal or less than 10 MHz with 25 pF loading at PAD.
4. The secondary power pair of V
DD
and V
SS
(pin 41 and pin 40 in 64-pin packages) and the third V
SS
(pin 13 in 64-pin packages) are not bonded
in 32-pin packages.
Figure 1. MCU block diagram
MC9S08PL60 Series Data Sheet, Rev. 3, 08/2019
4
NXP Semiconductors
Port H
CYCLIC REDUNDANCY
CHECK (CRC)
Port G
16-CH 10-BIT
ANALOG-TO-DIGITAL
CONVERTER(ADC)
Port F
Port E
Orderable part numbers
2 Orderable part numbers
The following table summarizes the part numbers of the devices covered by this
document.
Table 1. Ordering information
Part Number
CQH
Max. frequency
(MHz)
Flash memory
(KB)
RAM (KB)
EEPROM (B)
10-bit ADC
ACMP
16-bit FlexTimer
8-bit Modulo
timer
RTC
SCI (LIN
Capable)
Watchdog
CRC
KBI pins
GPIO
Package
20
60
4
256
16ch
1
6ch+2ch+2ch
1
Yes
3
Yes
Yes
16
57
64-QFP
MC9S08PL60
CLD
20
60
4
256
12ch
1
6ch+2ch+2ch
1
Yes
3
Yes
Yes
16
42
44-LQFP
CLC
20
60
4
256
12ch
1
6ch+2ch+2ch
1
Yes
3
Yes
Yes
13
30
32-LQFP
CQH
20
32
4
256
16ch
1
6ch+2ch+2ch
1
Yes
3
Yes
Yes
16
57
64-QFP
MC9S08PL32
CLD
20
32
4
256
12ch
1
6ch+2ch+2ch
1
Yes
3
Yes
Yes
16
42
44-LQFP
CLC
20
32
4
256
12ch
1
6ch+2ch+2ch
1
Yes
3
Yes
Yes
13
30
32-LQFP
3 Part identification
3.1 Description
Part numbers for the chip have fields that identify the specific part. You can use the
values of these fields to determine the specific part you have received.
3.2 Format
Part numbers for this device have the following format:
MC9S08PL60 Series Data Sheet, Rev. 3, 08/2019
NXP Semiconductors
5
微控制器 MCU
