Product Specification
PE9354
Product Description
The PE9354 SPDT high power UltraCMOS
®
RF switch is
designed to cover a broad range of applications from near
DC to 3000 MHz. This single-supply reflective switch
integrates on-board CMOS control logic driven by a simple,
single-pin CMOS and TTL compatible control input. Using a
nominal +3V power supply, a typical input P1dB
compression point of +31 dBm can be achieved. The
PE9354 also exhibits input-output isolation of better than
30 dB at 2000 MHz and is offered in a small 8-lead CFP.
The PE9354 is optimized for commercial space applications
and is manufactured on Peregrine’s UltraCMOS process, a
patented variation of silicon-on-insulator (SOI) technology
on a sapphire substrate, offering excellent RF performance
and intrinsic radiation tolerance. Single event latch-up (SEL)
is physically impossible and single event upset (SEU) is
better than 10
-9
errors per bit/day.
SPDT High Power UltraCMOS
®
RF Switch
Radiation Tolerant for Space
Applications
Features
•
Single +3V power supply
•
Low insertion loss: 0.55 dB @ 2000 MHz
•
High isolation of 30 dB @ 2000 MHz
•
Typical input P1dB compression point of
+31 dBm
•
100 kRad(Si) total dose
•
Single-pin CMOS or TTL logic control
•
Low cost
Figure 2. Package Type
8-lead CFP
Figure 1. Functional Diagram
DOC-02108
Table 1. AC Electrical Specifications @ –55 °C to +125 °C, V
DD
= 3.0V (Z
S
= Z
L
= 50Ω)
1
Parameter
Operation frequency
2
Insertion loss
Isolation – RFC to RF1/RF2
Isolation – RF1 to RF2
Return loss
3
Input P1dB compression point
Notes:
Condition
Min
DC
Typ
Max
3000
Unit
MHz
dB
dB
dB
dB
dBm
2000 MHz
2000 MHz
2000 MHz
2000 MHz
2000 MHz
28
28
24
0.55
32
28
22
31
0.80
1. Parameters are tested in production at –40 °C and +85 °C. Parameters are guaranteed through characterization at –55 °C, +25 °C and +125 °C.
2. Device linearity will begin to degrade below 10 MHz.
3. Return loss not measured in production due to equipment limitations.
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PE9354
Figure 3. Pin Configuration
Pin 1 dot marking
Table 4. Absolute Maximum Ratings
Symbol
V
DD
V
I
V
CTRL
T
ST
T
OP
P
IN
V
ESD
Parameter/Condition
Power supply voltage
Voltage on any input except
for the CTRL input
Voltage on CTRL input
Storage temperature range
Operating temperature range
Input power (50Ω)
ESD voltage
(Human Body Model)
Total cumulative exposure to
ionizing radiation
–65
–55
Min
–0.3
–0.3
Max
4.0
V
DD
+ 0.3
5.0
+150
+125
32
200
100
Unit
V
V
V
°C
°C
dBm
V
kRad(Si)
Table 2. Pin Descriptions
Pin #
1
2
Pin Name
V
DD
CTRL
Description
Nominal +3V supply connection.
CMOS or TTL logic level:
High = RFC to RF1 signal path.
Low = RFC to RF2 signal path.
Ground connection. Traces should be
physically short and connected to ground
plane for best performance.
Common RF port for switch.*
RF2 port.*
Ground connection. Traces should be
physically short and connected to ground
plane for best performance.
Ground connection. Traces should be
physically short and connected to ground
plane for best performance.
RF1 port.*
TID
3
4
5
6
GND
RFC
RF2
GND
Absolute maximum ratings are those values listed
in the above table. Exceeding these values may
cause permanent device damage. Functional
operation should be restricted to the limits in the
DC Electrical Specifications
table. Exposure to
absolute maximum ratings for extended periods
may affect device reliability.
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS device, observe
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the rating specified in
Table 3.
Latch-Up Immunity
Unlike conventional CMOS devices, UltraCMOS
devices are immune to latch-up.
Table 5. Control Logic Truth Table
Control Voltage
CTRL = CMOS or TTL High
CTRL = CMOS or TTL Low
Signal Path
RFC to RF1
RFC to RF2
7
8
GND
RF1
Note: * All RF pins must be DC blocked with an external series capacitor or
held at 0 VDC.
Table 3. DC Electrical Specifications
Parameter
Supply voltage, V
DD
Input leakage
Supply current, I
DD
(V
DD
= 3V, V
CTRL
= 3V)
Control voltage high
Control voltage low
0.7 × V
DD
0.3 × V
DD
Min
2.7
–1
28
Typ
3.0
Max
3.3
1
100
Unit
V
μA
μA
V
V
The control logic input pin (CTRL) is typically
driven by a +3V CMOS logic level signal, and has
a threshold of 50% of V
DD
. For flexibility to support
systems that have 5-volt control logic drivers, the
control logic input has been designed to handle a
5-volt logic HIGH signal. (A minimal current will be
sourced out of the V
DD
pin when the control logic
input voltage level exceeds V
DD
.)
Document No. DOC-26114-5│ UltraCMOS
®
RFIC Solutions
©2015 Peregrine Semiconductor Corp. All rights reserved.
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PE9354
Product Specification
Typical Performance Data @ –55 °C to +125 °C
Figure 4. Insertion Loss – RFC to RF1
Figure 5. Input P1dB Compression Point
Figure 6. Insertion Loss – RFC to RF2
Figure 7. Isolation – RFC to RF1
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PE9354
Typical Performance Data @ –55 °C to +125 °C (cont.)
Figure 8. Isolation – RFC to RF2
Figure 9. Isolation – RF1/RF2 to RF2/RF1
Figure 10. Return Loss – RFC
Figure 11. Return Loss – RF1, RF2
©2015 Peregrine Semiconductor Corp. All rights reserved.
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Document No. DOC-26114-5│ UltraCMOS
®
RFIC Solutions
PE9354
Product Specification
Evaluation Kit
The SPDT switch evaluation kit board was designed to
ease customer evaluation of the PE9354 SPDT switch.
The RF common port is connected through a 50Ω
transmission line to the top left SMA connector, J1. Port 1
and Port 2 are connected through 50Ω transmission lines
to the top two SMA connectors on the right side of the
board, J2 and J3. A through transmission line connects
SMA connectors J4 and J5. This transmission line can be
used to estimate the loss of the PCB over the
environmental conditions being evaluated.
The board is constructed of a two metal layer FR4
material with a total thickness of 0.031”. The bottom layer
provides ground for the RF transmission lines. The
transmission lines were designed using a coplanar
waveguide with ground plane model using a trace width
of 0.030”, trace gaps of 0.007”, dielectric thickness of
0.028”, metal thickness of 0.0014” and
ε
r
of 4.4.
J6 provides a means for controlling DC and digital inputs
to the device. Starting from the lower left pin, the second
pin to the right (J2–3) is connected to the device CTRL
input. The fourth pin to the right (J2–7) is connected to
the device V
DD
input. A decoupling capacitor (100 pF) is
provided on both CTRL and V
DD
traces. It is the
responsibility of the customer to determine proper supply
decoupling for their design application. Removing these
components from the evaluation board has not been
shown to degrade RF performance.
The ground plane has been removed from beneath the
device for performance issues. It was found that insertion
loss dips (suck-outs) were experienced due to the
capacitive effect of the metal package sitting insulated by
the solder-mask on the ground plane. All data specified
and shown on this datasheet was taken using this
evaluation board configuration. For optimal performance,
the package may be soldered directly to the ground
plane, but the reliability issues associated with this
mounting must be addressed by the customer.
Figure 12. Evaluation Board Layouts
PRT-17105
Figure 13. Evaluation Board Schematic
DOC-26126
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