DATASHEET
DDR and SDRAM Buffer
Description
DDR & SDRAM fanout buffer, for VIA Pro 266, KT266 and P4X266
DDR chipsets
ICS93718
Pin Configuration
FB_OUT
VDD3.3_2.5
GND
DDRT0_SDRAM0
DDRC0_SDRAM1
DDRT1_SDRAM2
DDRC1_SDRAM3
VDD3.3_2.5
GND
DDRT2_SDRAM4
DDRC2_SDRAM5
VDD3.3_2.5
BUF_IN
GND
DDRT3_SDRAM6
DDRC3_SDRAM7
VDD3.3_2.5
GND
DDRT4_SDRAM8
DDRC4_SDRAM9
DDRT5_SDRAM10
DDRC5_SDRAM11
VDD3.3_2.5
SDATA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
SEL_DDR*
VDD2.5
GND
DDRT11
DDRC11
DDRT10
DDRC10
VDD2.5
GND
DDRT9
DDRC9
VDD2.5
PD#*
GND
DDRT8
DDRC8
VDD2.5
GND
DDRT7
DDRC7
DDRT6
DDRC6
GND
SCLK
Output Features
•
•
•
•
•
•
•
•
Low skew, fanout buffer
1 to 12 differential clock distribution
I
2
C for functional and output control
Feedback pin for input to output synchronization
Supports up to 4 DDR DIMMs or 3 SDRAM DIMMs + 2
DDR DIMMs
Frequency supports up to 200MHz (DDR400)
Supports Power Down Mode for power mananagement
CMOS level control signal input
Key Specifications
•
•
•
•
•
OUTPUT - OUTPUT skew: <100ps
Output Rise and Fall Time for DDR outputs: 500ps - 700ps
DUTY CYCLE: 47% - 53%
48-pin SSOP package
Available in RoHS compliant packaging
48-Pin SSOP
*Internal Pull-up Resistor of 120K to VDD
Funtional Block Diagram
FB_OUT
DDRT0_SDRAM0
DDRC0_SDRAM1
DDRT1_SDRAM2
DDRC1_SDRAM3
Funtionality Table
MODE
DDR
Mode
DDR/SD
Mode
PIN 48
VDD
3.3_2.5
2.5V
PIN
4, 5, 6, 7, 10, 11, 15,
16, 19, 20, 21, 22
These outputs will be
DDR outputs
These outputs will be
standard SDRAM
outputs
BUF_IN
SEL_DDR=1
SCLK
SDATA
SEL_DDR*
PD#
Control
Logic
DDRT2_SDRAM4
DDRC2_SDRAM5
DDRT3_SDRAM6
DDRC3_SDRAM7
DDRT4_SDRAM8
DDRC4_SDRAM9
DDRT5_SDRAM10
DDRC5_SDRAM11
DDRT(11:6)
DDRC (11:6)
SEL_DDR=0
3.3V
IDT
TM
/ICS
TM
DDR and SDRAM buffer
ICS93718
ICS93718
REV E 02/11/07
ICS93718
DDR and SDRAM Buffer
Pin Description
PIN NUMBER
1
2, 8, 12, 17, 23,
3, 9, 14, 18, 26,
31, 35, 40, 46
45, 43, 39,
34, 30, 28,
44, 42, 38,
33, 29, 27,
21, 19, 15, 10, 6, 4
PIN NAME
FB_OUT
VDD3.3_2.5
GND
DDRT (11:6)
DDRC (11:6)
DDRT (5:0)
SDRAM (10, 8, 6, 4, 2, 0)
TYPE
OUT
PWR
PWR
OUT
OUT
OUT
OUT
IN
I/O
IN
PWR
DESCRIPTION
Feedback output, dedicated for external feedback
2.5V or 3.3V voltage supply to pins
4, 5, 6, 7, 10, 11, 15 , 16, 19 , 20, 21, 22
Ground
"Tr ue" Clock of differential pair outputs.
"Complementory" clocks of differential pair outputs.
"Tr ue" Clock of differential pair outputs, or 3.3V SDRAM
clock outputs depending on SEL_DDR input
"Complementory" clocks of differential pair outputs, or 3.3V
SDRAM clock outputs depending on SEL_DDR input
Single ended buffer input
Data pin for I
2
C circuitry 5V tolerant
Clock input of I
2
C input, 5V tolerant input
2.5V voltage supply
Asynchronous active low input pin used to power down the
device into a low power state. The inter nal clocks are
disabled. The latency of the power down will not be greater
t h a n 3 m s.
Select input for DDR mode or DDR/SD mode
0=DDR/SD mode 1=DDR mode
DDRC (5:0)
22, 20, 16, 11, 7, 5 SDRAM (11, 9, 7, 5, 3,
1,)
13
24
25
32, 37, 41, 47
BUF_IN
SDATA
SCLK
VDD2.5
36
PD#
IN
48
SEL_DDR
IN
IDT
TM
/ICS
TM
DDR and SDRAM Buffer
ICS93718
REV E 02/11/07
ICS93718
DDR and SDRAM Buffer
General I
2
C serial interface information
The information in this section assumes familiarity with I
2
C programming.
For more information, contact ICS for an I
2
C programming application note.
How to Write:
•
•
•
•
•
•
•
•
Controller (host) sends a start bit.
Controller (host) sends the write address D4
(H)
ICS clock will
acknowledge
Controller (host) sends a dummy command code
ICS clock will
acknowledge
Controller (host) sends a dummy byte count
ICS clock will
acknowledge
Controller (host) starts sending first byte (Byte 0)
through byte 6
• ICS clock will
acknowledge
each byte
one at a
time
.
• Controller (host) sends a Stop bit
How to Write:
Controller (Host)
Start Bit
Address
D4
(H)
Dummy Command Code
ACK
Dummy Byte Count
ACK
Byte 0
ACK
Byte 1
ACK
Byte 2
ACK
Byte 3
ACK
Byte 4
ACK
Byte 5
ACK
Byte 6
ACK
Byte 7
ACK
Stop Bit
ICS (Slave/Receiver)
How to Read:
•
•
•
•
•
•
Controller (host) will send start bit.
Controller (host) sends the read address D5
(H)
ICS clock will
acknowledge
ICS clock will send the
byte count
Controller (host) acknowledges
ICS clock sends first byte
(Byte 0) through byte
7
• Controller (host) will need to acknowledge each
byte
• Controller (host) will send a stop bit
How to Read:
Controller (Host)
Start Bit
Address
D5
(H)
ICS (Slave/Receiver)
ACK
ACK
Byte Count
ACK
Byte 0
ACK
Byte 1
ACK
Byte 2
ACK
Byte 3
ACK
Byte 4
ACK
Byte 5
ACK
Byte 6
ACK
Byte 7
Stop Bit
Notes:
1.
2.
3.
4.
5.
The ICS clock generator is a slave/receiver, I
2
C component. It can read back the data stored in the latches for verification.
Read-Back will support Intel PIIX4 "Block-Read" protocol.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
The input is operating at 3.3V logic levels.
The data byte format is 8 bit bytes.
To simplify the clock generator I
2
C interface, the protocol is set to use only "Block-Writes" from the controller. The bytes
must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been
transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those two bytes.
The data is loaded until a Stop sequence is issued.
At power-on, all registers are set to a default condition, as shown.
ICS93718
REV E 02/11/07
6.
IDT
TM
/ICS
TM
DDR and SDRAM Buffer
ICS93718
DDR and SDRAM Buffer
Byte 6: Output Control
(1= enable, 0 = disable)
Byte 7: Output Control
(1= enable, 0 = disable)
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
48
-
-
-
45, 44
43, 42
39, 38
34, 33
PWD
1
1
1
1
1
1
1
1
DESCRIPTION
SEL_DDR (Read back only)
(Reserved)
(Reserved)
(Reserved)
DDRT11, DDRC11
DDRT10, DDRC10
DDRT9, DDRC9
DDRT8, DDRC8
BIT
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PIN#
30, 29
28, 27
21, 22
19, 20
15, 16
10, 11
6, 7
4, 5
PWD
DESCRIPTION
1 DDRT7, DDRC7
1 DDRT6, DDRC6
DDRT5, SDRAM10
1
DDRC5_SDRAM11
DDRT4_SDRAM8
1
DDRC4_SDRAM9
DDRT3_SDRAM6
1
DDRC3_SDRAM7
DDRT2_SDRAM4
1
DDRC2_SDRAM5
DDRT1_SDRAM2
1
DDRC1_SDRAM3
DDRT0_SDRAM1
1
DDRC0_SDRAM0
IDT
TM
/ICS
TM
DDR and SDRAM Buffer
ICS93718
REV E 02/11/07
ICS93718
DDR and SDRAM Buffer
Absolute Max
Supply Voltage (VDD & VDD2.5)
Logic Inputs
Ambient Operating Temperature
Case Temperature
Storage Temperature
-0.5V to 3.6V
GND –0.5 V to V
DD
+0.5 V
0°C to +85°C
115°C
–65°C to +150°C
Stresses above those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
SEL_DDR = 0 SDRAM Outputs
V
DD
= 3.3V, T
A
= 0 - 85°C; (unless otherwise stated)
PARAMETER
Input High Current
Input Low Current
SYMBOL
CONDITIONS
I
IH
V
I
= V
DD
or GND
I
IL
V
I =
V
DD
or GND
I
DD3.3_2.5
C
L
= 0pf, 133MHz
Operating Supply Current I
DD2.5
C
L
= 0pf, 133MHz
I
DDPD
C
L
= 0pf, all frequencies
Output High Current
I
OH
V
DD
= 3.3V
,
V
OUT
= 1V
Output Low Current
I
OL
V
DD
= 3.3V
,
V
OUT
= 1.2V
V
DD
= 3.3V,
V
OH
= -12mA
V
DD
= 3.3V
I
OH
= 12mA
V
I
=
MIN
-100
TYP
1
-20
200
100
3
-74
MAX
10
250
200
10
-18
UNITS
µA
µA
mA
mA
mA
mA
mA
V
26
2
42
2.95
0.35
2
0.4
High-level output voltage V
OH
Low-level output voltage
Input Capacitance
1
1
V
OL
C
IN
GND or V
DD
pF
Guaranteed by design, not 100% tested in production.
Recommended Operating Condition
SEL_DDR=0 SDRAM Outputs V
DD
=3.3V
, T
A
= 0 - 85°C; (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
3.0
3.3
V
DD3.3_2.5
Power Supply Voltage
V
DD2.5
2.3
2.5
SEL_DDR, PD# input
2.0
Input High Voltage
V
IH
Input Low Voltage
Input voltage level
1
MAX
3.6
2.7
0.8
UNITS
V
V
V
V
V
IL
V
IN
SEL_DDR, PD# input
V
DD
Guaranteed by design, not 100% tested in production.
IDT
TM
/ICS
TM
DDR and SDRAM Buffer
ICS93718
REV E 02/11/07
嵌入式系统
