93LC76/86
8K/16K 2.5V CMOS Serial EEPROM
FEATURES
• Single supply with programming operation down
to 2.5V
• Low power CMOS technology
- 1 mA active current typical
- 5
µA
standby current (typical) at 3.0V
• ORG pin selectable memory configuration
1024 x 8 or 512 x 16 bit organization (93LC76)
2048 x 8 or 1024 x 16 bit organization (93LC86)
• Self-timed ERASE and WRITE cycles
(including auto-erase)
• Automatic ERAL before WRAL
• Power on/off data protection circuitry
• Industry standard 3-wire serial I/O
• Device status signal during ERASE/WRITE
cycles
• Sequential READ function
• 10,000,000 ERASE/WRITE cycles
guaranteed
• Data retention > 200 years
• 8-pin PDIP/SOIC package
• Temperature ranges available:
- Commercial (C): 0°C to +70°C
- Industrial (I):
-40°C to +85°C
PIN CONFIGURATION
DIP Package
93LC76/86
CS
CLK
DI
DO
VCC
PE
ORG
VSS
SOIC Package
93LC76/86
CS
CLK
DI
DO
VCC
PE
ORG
VSS
BLOCK DIAGRAM
V
CC
V
SS
DESCRIPTION
The Microchip Technology Inc. 93LC76/86 are 8K and
16K low voltage serial Electrically Erasable PROMs.
The device memory is configured as x8 or x16 bits
depending on the ORG pin setup. Advanced CMOS
technology makes these devices ideal for low power
non-volatile memory applications. These devices also
have a Program Enable (PE) pin to allow the user to
write protect the entire contents of the memory array.
The 93LC76/86 is available in standard 8-pin DIP and
8-pin surface mount SOIC packages.
Memory
Array
Address
Decoder
Address
Counter
Data
Register
DI
Output
Buffer
DO
PE
CS
Mode
Decode
Logic
CLK
Clock
Generator
©
1995 Microchip Technology Inc.
Preliminary
DS21131A-page 1
93LC76/86
1.0 ELECTRICAL CHARACTERISTICS
Maximum Ratings*
V
CC
........................................................................7.0V
All inputs and outputs w.r.t. V
SS
.... -0.6V to Vcc +1.0V
Storage temperature ..........................-65°C to +150°C
Ambient temp. with power applied .....-65°C to +125°C
Soldering temperature of leads (10 seconds) .. +300°C
ESD protection on all pins ..................................... 4 kV
*Notice: Stresses above those listed under “Maximum ratings”
may cause permanent damage to the device. This is a stress rat-
ing only and functional operation of the device at those or any
other conditions above those indicated in the operational listings
of this specification is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability
AC Test Conditions
Input Pulse Levels
Output Reference Levels
PIN FUNCTION TABLE
Name
CS
CLK
DI
DO
V
SS
ORG
PE
V
CC
Chip Select
Serial Data Clock
Serial Data Input
Serial Data Output
Ground
Memory Configuration
Program Enable
Power Supply
Function
0.4V to 2.4V
0.8V and 2.0V
TABLE 1-1:
D.C. CHARACTERISTICS
Applicable over recommended operating ranges shown below unless otherwise noted:
Commercial (C): Tamb = 0°C to +70°C
Industrial (I):
Tamb = -40°C to +85°C
V
CC
= +2.5V to +6.0V
Parameter
High level input voltage
Symbol
V
IH1
V
IH2
Low level input voltage
V
IL1
V
IL2
Low level output voltage
V
OL1
V
OL2
High level output voltage
V
OH1
V
OH2
Input leakage current
Output leakage current
Pin capacitance
(all inputs/outputs)
Operating current
I
LI
I
LO
C
INT
I
CC
write
I
CC
read
Standby current
I
CCS
Min.
2.0
0.7 V
CC
-0.3
-0.3
—
—
2.4
V
CC
-0.2
-10
-10
—
—
—
—
Max.
V
CC
+1
V
CC
+1
0.8
0.2 V
CC
0.4
0.2
—
—
10
10
7
3
1
500
100
30
Units
V
V
V
V
V
V
V
V
µA
µA
pF
mA
mA
µA
µA
µA
Conditions
V
CC
≥
2.7V
V
CC
< 2.7V
V
CC
≥
2.7V
V
CC
< 2.7V
I
OL
= 2.1 mA; V
CC
= 4.5V
I
OL
=100
µA;
V
CC
= V
CC
Min.
I
OH
= -400
µA;
V
CC
= 4.5V
I
OH
= -100
µA;
V
CC
= V
CC
Min.
V
IN
= 0.1V to V
CC
V
OUT
= 0.1V to V
CC
(Note 1)
Tamb = +25°C, F
CLK
= 1 MHz
F
CLK
= 3 MHz; V
CC
= 6.0V
F
CLK
= 3 MHz; V
CC
= 6.0V
F
CLK
= 1 MHz; V
CC
= 3.0V
CLK = CS = 0V; V
CC
= 6.0V
CLK = CS = 0V; V
CC
= 3.0V
Note 1:
This parameter is periodically sampled and not 100% tested.
DS21131A-page 2
Preliminary
©
1995 Microchip Technology Inc.
93LC76/86
TABLE 1-2:
A.C. CHARACTERISTICS
Applicable over recommended operating ranges shown below unless otherwise noted:
Commercial (C): Tamb = 0°C to +70°C
Industrial (I):
Tamb = -40°C to +85°C
V
CC
= +2.5V to +6.0V
Parameter
Clock frequency
Clock high time
Clock low time
Chip select setup time
Chip select hold time
Chip select low time
Data input setup time
Data input hold time
Data output delay time
Data output disable time
Status valid time
Program cycle time
Symbol
F
CLK
T
CKH
T
CKL
T
CSS
T
CSH
T
CSL
T
DIS
T
DIH
T
PD
T
CZ
TSV
T
WC
T
EC
T
WL
Min.
—
100
250
100
250
50
100
0
250
50
100
50
100
—
—
—
—
—
—
Max.
3
1
—
—
—
—
—
—
—
100
250
100
500
100
250
5
15
30
Units
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ms
ms
Relative to CLK
4.5V
≤
V
CC
≤
6.0V, Relative to CLK
2.5V
≤
V
CC
<4.5V, Relative to CLK
4.5V
2.5V
4.5V
2.5V
4.5V
≤
V
CC
≤
V
CC
≤
V
CC
≤
V
CC
≤
V
CC
≤
6.0V, Relative to CLK
<
4.5V, Relative to CLK
≤
6.0V, C
L
= 100 pF
< 4.5V, C
L
= 100 pF
≤
6.0V
Conditions
4.5V
≤
V
CC
≤
6.0V
2.5V
≤
V
CC
<
4.5V
4.5V
≤
V
CC
≤
6.0V
2.5V
≤
V
CC
<
4.5V
4.5V
≤
V
CC
≤
6.0V
2.5V
≤
V
CC
<
4.5V
4.5V
≤
V
CC
≤
6.0V, Relative to CLK
2.5V
≤
V
CC
<
4.5V, Relative to CLK
2.5V
≤
V
CC
< 4.5V (Note 2)
4.5V
≤
V
CC
≤
6.0V, C
L
= 100 pF
2.5V
≤
V
CC
<4.5V, C
L
= 100 pF
ERASE/WRITE mode
ERAL mode
WRAL mode
Note 2:
This parameter is periodically sampled and not 100% tested.
©
1995 Microchip Technology Inc.
Preliminary
DS21131A-page 3
93LC76/86
2.0
2.1
PIN DESCRIPTIONS
Chip Select (CS)
2.3
Data In (DI)
Data In is used to clock in a START bit, opcode,
address, and data synchronously with the CLK input.
A HIGH level selects the device. A LOW level deselects
the device and forces it into standby mode. However, a
programming cycle which is already initiated will be
completed, regardless of the CS input signal. If CS is
brought LOW during a program cycle, the device will go
into standby mode as soon as the programming cycle
is completed.
CS must be LOW for 250 ns minimum (T
CSL
) between
consecutive instructions. If CS is LOW, the internal
control logic is held in a RESET status.
2.4
Data Out (DO)
Data Out is used in the READ mode to output data syn-
chronously with the CLK input (T
PD
after the positive
edge of CLK).
This pin also provides READY/BUSY status informa-
tion during ERASE and WRITE cycles. READY/BUSY
status information is available when CS is high. It will
be displayed until the next start bit occurs as long as
CS stays high.
2.2
Serial Clock (CLK)
2.5
Organization (ORG)
The Serial Clock is used to synchronize the communi-
cation between a master device and the 93LC76/86.
Opcode, address, and data bits are clocked in on the
positive edge of CLK. Data bits are also clocked out on
the positive edge of CLK.
CLK can be stopped anywhere in the transmission
sequence (at HIGH or LOW level) and can be contin-
ued anytime with respect to clock HIGH time (T
CKH
)
and clock LOW time (T
CKL
). This gives the controlling
master freedom in preparing opcode, address, and
data.
CLK is a “Don't Care” if CS is LOW (device deselected).
If CS is HIGH, but START condition has not been
detected, any number of clock cycles can be received
by the device without changing its status (i.e., waiting
for START condition).
CLK cycles are not required during the self-timed
WRITE (i.e., auto ERASE/WRITE) cycle.
After detection of a start condition the specified number
of clock cycles (respectively LOW to HIGH transitions
of CLK) must be provided. These clock cycles are
required to clock in all opcode, address, and data bits
before an instruction is executed (see Table 2-1
through Table 2-4 for more details). CLK and DI then
become don't care inputs waiting for a new start condi-
tion to be detected.
Note:
CS must go LOW between consecutive
instructions, except when performing a
sequential read (Refer to Section 4.1 for
more detail on sequential reads).
When ORG is connected to V
CC
, the x16 memory orga-
nization is selected. When ORG is tied to V
SS
, the x8
memory organization is selected. There is an internal
pull-up resistor on the ORG pin that will select x16
organization when left unconnected.
2.6
Program Enable (PE)
This pin allows the user to enable or disable the ability
to write data to the memory array. If the PE pin is
floated or tied to V
CC
, the device can be programmed.
If the PE pin is tied to V
SS
, programming will be inhib-
ited. There is an internal pull-up on this device that
enables programming if this pin is left floating.
DS21131A-page 4
Preliminary
©
1995 Microchip Technology Inc.
93LC76/86
Table 2-1:
Instruction
READ
EWEN
ERASE
ERAL
WRITE
WRAL
EWDS
INSTRUCTION SET FOR 93LC76: ORG=1 (x16 ORGANIZATION)
SB
1
1
1
1
1
1
1
Opcode
10
00
11
00
01
00
00
Address
X A8 A7 A6 A5 A4 A3 A2 A1 A0
1 1 X X X X X X X X
X A8 A7 A6 A5 A4 A3 A2 A1 A0
1 0 X X X X X X X X
X A8 A7 A6 A5 A4 A3 A2 A1 A0
0 1 X X X X X X X X
0 0 X X X X X X X X
Data In
—
—
—
—
D15 - D0
D15 - D0
—
Data Out
D15 - D0
High-Z
(RDY/BSY)
(RDY/BSY)
(RDY/BSY)
(RDY/BSY)
High-Z
Req. CLK Cycles
29
13
13
13
29
29
13
Table 2-2:
Instruction
READ
EWEN
ERASE
ERAL
WRITE
WRAL
EWDS
INSTRUCTION SET FOR 93LC76: ORG=0 (x8 ORGANIZATION)
SB
1
1
1
1
1
1
1
Opcode
10
00
11
00
01
00
00
Address
X A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
1 1 X X X X X X X X
X A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
1 0 X X X X X X X
X
Data In
—
—
—
—
D7 - D0
D7 - D0
—
Data Out
D7 - D0
High-Z
(RDY/BSY)
(RDY/BSY)
(RDY/BSY)
(RDY/BSY)
High-Z
Req. CLK
Cycles
22
14
14
14
22
22
14
X A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
0 1 X X X X X X X
0 0 X X X X X X X
X
X
©
1995 Microchip Technology Inc.
Preliminary
DS21131A-page 5
