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952607YFT

Processor Specific Clock Generator, 400MHz, CMOS, PDSO48

器件类别:嵌入式处理器和控制器    微控制器和处理器   

厂商名称:IDT (Integrated Device Technology)

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器件参数
参数名称
属性值
是否Rohs认证
不符合
厂商名称
IDT (Integrated Device Technology)
包装说明
SSOP,
Reach Compliance Code
compli
ECCN代码
EAR99
JESD-30 代码
R-PDSO-G48
JESD-609代码
e0
长度
15.875 mm
端子数量
48
最高工作温度
70 °C
最低工作温度
最大输出时钟频率
400 MHz
封装主体材料
PLASTIC/EPOXY
封装代码
SSOP
封装形状
RECTANGULAR
封装形式
SMALL OUTLINE, SHRINK PITCH
峰值回流温度(摄氏度)
225
主时钟/晶体标称频率
14.31818 MHz
认证状态
Not Qualified
座面最大高度
2.8 mm
最大供电电压
3.465 V
最小供电电压
3.135 V
标称供电电压
3.3 V
表面贴装
YES
技术
CMOS
温度等级
COMMERCIAL
端子面层
Tin/Lead (Sn/Pb)
端子形式
GULL WING
端子节距
0.635 mm
端子位置
DUAL
处于峰值回流温度下的最长时间
30
宽度
7.5 mm
uPs/uCs/外围集成电路类型
CLOCK GENERATOR, PROCESSOR SPECIFIC
文档预览
Integrated
Circuit
Systems, Inc.
ICS952607
Programmable Timing Control Hub™ for Next Gen P4™ processor
Recommended Application:
CK409 Compliant clock for Next Gen P4 Processor
Output Features:
2 - 0.7V current-mode differential CPU pairs
1 - 0.7V current-mode differential SRC pair
9 - PCI, 3 free running, 33MHz
3 - REF, 14.318MHz
3 - 3V66, 66.66MHz
1 - VCH/3V66, selectable 48MHz or 66MHz
2 - 48MHz
1 - 24/48MHz
Key Specifications:
CPU/SRC outputs cycle-cycle jitter < 125ps
3V66 outputs cycle-cycle jitter < 250ps
PCI outputs cycle-cycle jitter < 250ps
+/- 300ppm frequency accuracy on CPU & SRC clocks
Features/Benefits:
QuadRom
TM
frequency selection.
Programmable output frequency.
Programmable asynchronous 3V66&PCI frequency.
Programmable output divider ratios.
Programmable output rise/fall time.
Programmable output skew.
Programmable spread percentage for EMI control.
Watchdog timer technology to reset system if system
malfunctions.
Programmable watch dog safe frequency.
Support I2C Index read/write and block read/write
operations.
Uses external 14.318MHz reference input.
Supports tight ppm accuracy clocks for Serial-ATA
Supports spread spectrum modulation, 0 to -0.5%
down spread and +/- 0.25% center spread
Supports CPU clks up to 400MHz
Functionality
Bit4 Bit3 Bit2 Bit1 Bit0
FS4 FS3 FS2 FS1 FS0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
1
1
0
0
1
0
0
0
0
1
0
1
0
0
1
1
0
0
0
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CPU
MHz
100.00
200.00
133.33
166.67
200.00
400.00
266.67
333.33
100.99
201.98
134.65
168.31
115.00
230.00
153.33
191.67
100.00
200.00
133.33
166.67
200.00
400.00
266.67
333.33
105.00
210.00
140.00
175.00
110.00
220.00
146.66
183.34
AGP
MHz
66.66
66.66
66.66
66.66
66.66
66.66
66.66
66.66
67.33
67.33
67.33
67.32
76.66
76.66
76.66
76.66
66.66
66.66
66.66
71.43
66.66
66.66
66.66
66.66
69.99
69.99
69.99
69.99
73.33
73.33
73.33
73.33
PCI
MHz
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.66
33.66
33.66
33.66
38.33
38.33
38.33
38.33
33.33
33.33
33.33
35.71
33.33
33.33
33.33
33.33
35.00
35.00
35.00
35.00
36.66
36.66
36.66
36.66
Pin Configuration
*FS1/REF0
1
48 VDDA
*FS0/REF1
2
47 GND
REF2
3
46 IREF
VDDREF
4
45 Reset#
X1
5
44 GND
X2
6
43 CPUCLKT1
GND
7
42 CPUCLKC1
**FS2/PCICLK_F0
8
41 VDDCPU
**FS4/PCICLK_F1
9
40 CPUCLKT0
PCICLK_F2 10
39 CPUCLKC0
38 GND
VDDPCI 11
12
37 SRCCLKT
GND
36 SRCCLKC
^^PCICLK0 13
14
35 VDD
PCICLK1
34 VttPWR_GD/PD#
PCICLK2 15
16
33 SDATA
PCICLK3
32 SCLK
VDDPCI 17
18
31 3V66_0
GND
30 3V66_1
PCICLK4 19
20
29 GND
PCICLK5
**Sel24_48#/24_48MHz 21
28 VDD3V66
22
27 3V66_2
**FS3/48MHz_0
26 3V66_3/VCH
48MHz_1 23
24
25 VDD48
GND
* This pin have 120K pull-up to VDD
** This pin have 120K pull-down to GND
^^ An external 2.2K pull-down resistor is needed on this pin
ICS952607
48-pin SSOP
Note: FS1 and FS0 are equal to Intel CK409-defined FSA and FSB,
respectively.
0734A—A07/26/05
Integrated
Circuit
Systems, Inc.
ICS952607
Pin Description
PIN # PIN NAME
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
*FS1/REF0
*FS0/REF1
REF2
VDDREF
X1
X2
GND
**FS2/PCICLK_F0
**FS4/PCICLK_F1
PCICLK_F2
VDDPCI
GND
^^PCICLK0
PCICLK1
PCICLK2
PCICLK3
VDDPCI
GND
PCICLK4
PCICLK5
**Sel24_48#/24_48MHz
**FS3/48MHz_0
48MHz_1
GND
VDD48
3V66_3/VCH
3V66_2
VDD3V66
GND
3V66_1
3V66_0
SCLK
SDATA
VttPWR_GD/PD#
VDD
SRCCLKC
SRCCLKT
GND
CPUCLKC0
CPUCLKT0
VDDCPU
CPUCLKC1
CPUCLKT1
GND
Reset#
IREF
GND
VDDA
PIN TYPE
I/O
I/O
OUT
PWR
IN
OUT
PWR
I/O
I/O
OUT
PWR
PWR
OUT
OUT
OUT
OUT
PWR
PWR
OUT
OUT
I/O
I/O
OUT
PWR
PWR
OUT
OUT
PWR
PWR
OUT
OUT
IN
I/O
IN
PWR
OUT
OUT
PWR
OUT
OUT
PWR
OUT
OUT
PWR
OUT
OUT
PWR
PWR
DESCRIPTION
Frequency select latch input pin / 14.318 MHz reference clock.
Frequency select latch input pin / 14.318 MHz reference clock.
14.318 MHz reference clock.
Ref, XTAL power supply, nominal 3.3V
Crystal input,nominally 14.318MHz.
Crystal output, Nominally 14.318MHz
Ground pin.
Frequency select latch input pin / 3.3V PCI free running clock output.
Frequency select latch input pin / 3.3V PCI free running clock output.
Free running PCI clock not affected by PCI_STOP# .
Power supply for PCI clocks, nominal 3.3V
Ground pin.
PCI clock output.
PCI clock output.
PCI clock output.
PCI clock output.
Power supply for PCI clocks, nominal 3.3V
Ground pin.
PCI clock output.
PCI clock output.
Latched select input for 24/48MHz output / 24/48MHz clock output. 1=24mHz, 0 = 48MHz.
Frequency select latch input pin / Fixed 48MHz clock output. 3.3V
48MHz clock output.
Ground pin.
Power for 24 & 48MHz output buffers and fixed PLL core.
3.3V 66.66MHz clock output / 48MHz VCH clock output.
3.3V 66.66MHz clock output
Power pin for the 3V66 clocks.
Ground pin.
3.3V 66.66MHz clock output
3.3V 66.66MHz clock output
Clock pin of I2C circuitry 5V tolerant
Data pin for I2C circuitry 5V tolerant
This 3.3V LVTTL input is a level sensitive strobe used to determine when latch inputs are
valid and are ready to be sampled. This is an active high input. / Asynchronous active low
input pin used to power down the device into a low power state.
Power supply, nominal 3.3V
Complement clock of differential pair for S-ATA support.
+/- 300ppm accuracy required.
True clock of differential pair for S-ATA support.
+/- 300ppm accuracy required.
Ground pin.
"Complementary" clocks of differential pair CPU outputs. These are current mode outputs.
External resistors are required for voltage bias.
"True" clocks of differential pair CPU outputs. These are current mode outputs. External
resistors are required for voltage bias.
Supply for CPU clocks, 3.3V nominal
"Complementary" clocks of differential pair CPU outputs. These are current mode outputs.
External resistors are required for voltage bias.
"True" clocks of differential pair CPU outputs. These are current mode outputs. External
resistors are required for voltage bias.
Ground pin.
Real time system reset signal for frequency gear ratio change or watchdog timer timeout.
This signal is active low.
This pin establishes the reference current for the CPUCLK pairs. This pin requires a fixed
precision resistor tied to ground in order to establish the appropriate current.
Ground pin.
3.3V power for the PLL core.
0734A—07/26/05
2
Integrated
Circuit
Systems, Inc.
ICS952607
General Description
ICS952607
is a 48 pin clock chip following Intel CK409 Yellow Cover specification. This clock synthesizer provides a single
chip solution for next generation P4 Intel processors and Intel chipsets.
ICS952607
is driven with a 14.318MHz crystal. It
generates CPU outputs up to 200MHz. It also provides a tight ppm accuracy output for Serial ATA suuport.
The
ICS952607
is part of a whole new line of ICS clock generators and buffers called TCH™ (Timing Control Hub). This part
incorporates ICS's newest clock technology which offers more robust features and functionality. Employing the use of a
serially programmable I
2
C interface, this device can adjust the output clocks by configuring the frequency setting, the output
divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each
individual output clock. M/N control can configure output frequency with resolution up to 0.1MHz increment. This part also
provides 128 frequency selections via ICS QuadROM
TM
technology as an alternate to M/N programming.
Block Diagram
Frequency
Dividers
PLL2
48MHz (1:0)
24_48MHz
X1
X2
XTAL
REF (2:0)
CPUCLKT (1:0)
SCLK
SDATA
VTTPWRGD#
PD#
FS (4:0)
Sel24_48#
Control
Logic
Programmable
Spread
PLL1
Programmable
Frequency
Dividers
CPUCLKC (1:0)
STOP
Logic
SRCCLKT
SRCCLKC
3V66 (3:0)
PCICLK (5:0)
PCICLK_F (2:0)
RESET#
I REF
Power Groups
Pin Number
VDD
GND
4
7
28
29
11,17
12,18
35
38
41
44
48
47
25
24
Description
Xtal, Ref
3V66
PCICLK outputs
SRCCLK outputs
CPU outputs
MCLK, CPU Analog, CPU digital
48MHz Fix, Fix Digital, Fix analog
0734A—07/26/05
3
Integrated
Circuit
Systems, Inc.
ICS952607
Table1: QuadRom Frequency Selection Table
Bit6 Bit5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Bit4 Bit3 Bit2 Bit1 Bit0
FS4 FS3 FS2 FS1 FS0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CPU
MHz
100.00
200.00
133.33
166.67
200.00
400.00
266.67
333.33
100.99
201.98
134.65
168.31
115.00
230.00
153.33
191.67
100.00
200.00
133.33
166.67
200.00
400.00
266.67
333.33
105.00
210.00
140.00
175.00
110.00
220.00
146.66
183.34
AGP
MHz
66.66
66.66
66.66
66.66
66.66
66.66
66.66
66.66
67.33
67.33
67.33
67.32
76.66
76.66
76.66
76.66
66.66
66.66
66.66
71.43
66.66
66.66
66.66
66.66
69.99
69.99
69.99
69.99
73.33
73.33
73.33
73.33
PCI
MHz
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.66
33.66
33.66
33.66
38.33
38.33
38.33
38.33
33.33
33.33
33.33
35.71
33.33
33.33
33.33
33.33
35.00
35.00
35.00
35.00
36.66
36.66
36.66
36.66
Spread
%
0 to -0.5% Down
0 to -0.5% Down
0 to -0.5% Down
0 to -0.5% Down
0 to -0.5% Down
0 to -0.5% Down
0 to -0.5% Down
0 to -0.5% Down
0.35% Center
0.35% Center
0.35% Center
0.35% Center
No Spread
No Spread
No Spread
No Spread
0.35% Center
0.35% Center
0.35% Center
0.35% Center
0.35% Center
0.35% Center
0.35% Center
0.35% Center
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
Table continued on next page.
0734A—07/26/05
4
Integrated
Circuit
Systems, Inc.
ICS952607
Table1: QuadRom Frequency Selection Table (Continued)
Bit6 Bit5
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Bit4 Bit3 Bit2 Bit1 Bit0
FS4 FS3 FS2 FS1 FS0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
1
1
0
0
1
0
0
0
0
1
0
1
0
0
1
1
0
0
0
1
1
1
0
1
0
0
0
0
1
0
0
1
0
1
0
1
0
0
1
0
1
1
0
1
1
0
0
0
1
1
0
1
0
1
1
1
0
0
1
1
1
1
1
0
0
0
0
1
0
0
0
1
1
0
0
1
0
1
0
0
1
1
1
0
1
0
0
1
0
1
0
1
1
0
1
1
0
1
0
1
1
1
1
1
0
0
0
1
1
0
0
1
1
1
0
1
0
1
1
0
1
1
1
1
1
0
0
1
1
1
0
1
1
1
1
1
0
1
1
1
1
1
CPU
MHz
103.00
206.00
137.33
171.67
228.89
412.00
274.67
343.33
105.00
210.00
140.00
175.00
233.33
420.00
280.00
350.00
107.00
214.00
142.66
178.34
237.78
428.00
285.34
356.66
110.00
220.00
146.66
183.34
244.44
440.00
293.34
366.66
AGP
MHz
68.66
68.66
68.66
68.66
68.66
68.66
68.66
68.66
69.99
69.99
69.99
69.99
69.99
69.99
69.99
69.99
71.33
71.33
71.33
71.33
71.33
71.33
71.33
71.33
73.33
73.33
73.33
73.33
73.33
73.33
73.33
73.33
PCI
MHz
34.33
34.33
34.33
34.33
34.33
34.33
34.33
34.33
35.00
35.00
35.00
35.00
35.00
35.00
35.00
35.00
35.66
35.66
35.66
35.66
35.66
35.66
35.66
35.66
36.66
36.66
36.66
36.66
36.66
36.66
36.66
36.66
Spread
%
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
No Spread
Table continued on next page.
0734A—07/26/05
5
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参数对比
与952607YFT相近的元器件有:ICS952607YF-T、ICS952607YFT。描述及对比如下:
型号 952607YFT ICS952607YF-T ICS952607YFT
描述 Processor Specific Clock Generator, 400MHz, CMOS, PDSO48 Processor Specific Clock Generator, 400MHz, PDSO48, MO-118, SSOP-48 Processor Specific Clock Generator, 400MHz, PDSO48, MO-118, SSOP-48
是否Rohs认证 不符合 不符合 不符合
厂商名称 IDT (Integrated Device Technology) IDT (Integrated Device Technology) IDT (Integrated Device Technology)
包装说明 SSOP, SSOP, SSOP,
Reach Compliance Code compli unknown compliant
ECCN代码 EAR99 EAR99 EAR99
JESD-30 代码 R-PDSO-G48 R-PDSO-G48 R-PDSO-G48
JESD-609代码 e0 e0 e0
长度 15.875 mm 15.875 mm 15.875 mm
端子数量 48 48 48
最高工作温度 70 °C 70 °C 70 °C
最大输出时钟频率 400 MHz 400 MHz 400 MHz
封装主体材料 PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
封装代码 SSOP SSOP SSOP
封装形状 RECTANGULAR RECTANGULAR RECTANGULAR
封装形式 SMALL OUTLINE, SHRINK PITCH SMALL OUTLINE, SHRINK PITCH SMALL OUTLINE, SHRINK PITCH
峰值回流温度(摄氏度) 225 NOT SPECIFIED 225
主时钟/晶体标称频率 14.31818 MHz 14.31818 MHz 14.31818 MHz
认证状态 Not Qualified Not Qualified Not Qualified
座面最大高度 2.8 mm 2.8 mm 2.8 mm
最大供电电压 3.465 V 3.465 V 3.465 V
最小供电电压 3.135 V 3.135 V 3.135 V
标称供电电压 3.3 V 3.3 V 3.3 V
表面贴装 YES YES YES
技术 CMOS CMOS CMOS
温度等级 COMMERCIAL COMMERCIAL COMMERCIAL
端子面层 Tin/Lead (Sn/Pb) TIN LEAD Tin/Lead (Sn/Pb)
端子形式 GULL WING GULL WING GULL WING
端子节距 0.635 mm 0.635 mm 0.635 mm
端子位置 DUAL DUAL DUAL
处于峰值回流温度下的最长时间 30 NOT SPECIFIED 30
宽度 7.5 mm 7.5 mm 7.5 mm
uPs/uCs/外围集成电路类型 CLOCK GENERATOR, PROCESSOR SPECIFIC CLOCK GENERATOR, PROCESSOR SPECIFIC CLOCK GENERATOR, PROCESSOR SPECIFIC
是否无铅 - 含铅 含铅
零件包装代码 - SSOP SSOP
针数 - 48 48
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器件捷径:
00 01 02 03 04 05 06 07 08 09 0A 0C 0F 0J 0L 0M 0R 0S 0T 0Z 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1H 1K 1M 1N 1P 1S 1T 1V 1X 1Z 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 2G 2K 2M 2N 2P 2Q 2R 2S 2T 2W 2Z 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 3G 3H 3J 3K 3L 3M 3N 3P 3R 3S 3T 3V 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4M 4N 4P 4S 4T 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5E 5G 5H 5K 5M 5N 5P 5S 5T 5V 60 61 62 63 64 65 66 67 68 69 6A 6C 6E 6F 6M 6N 6P 6R 6S 6T 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7M 7N 7P 7Q 7V 7W 7X 80 81 82 83 84 85 86 87 88 89 8A 8D 8E 8L 8N 8P 8S 8T 8W 8Y 8Z 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9F 9G 9H 9L 9S 9T 9W
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