Electronics, Inc.
2590 North First Street, San Jose, CA 95131, U.S.A.
Tel: 408-732-5000
Fax: 408-732-5055
http://www.atpinc.com
Rev
. Date:
Jun. 09, 2017
ATP A4B04QG8BLRCSW
4GB DDR4-2400 Wide Temperature
VLP REGISTERED ECC DIMM
DESCRIPTION
The ATP A4B04QG8BLRCSW is a high performance 4GB DDR4-2400 VLP (Very Low Profile) Registered
ECC SDRAM memory module. It is organized as 512M x 72 in a 288-pin Dual-In-Line Memory Module
(DIMM) package. The module utilizes nine 512Mx8 DDR4 SDRAMs in FBGA package. The module
consists of a 512-byte serial EEPROM, which contains the module configuration information.
KEY FEATURES
High Density: 4GB (512M x 72)
DIMM Rank: 1 Rank
Cycle Time: 0.83ns (1200MHz)
CAS Latency: 17(DDR4-2400), 15(DDR4-2133)
Power supply: V
DD
=1.2V ± 0.06V
V
PP
=2.5V± 0.125V
V
DDSPD
=2.2V~3.6V
Support ECC error detection and correction
Nominal and dynamic on-die termination(ODT) for data, strobe, and mask signals
Low-power auto self refresh (LPASR)
Data bus inversion(DBI) for data bus
16 internal banks(x8); 4 groups of 4 banks each
Internal self calibration through ZQ
Temperature controlled refresh (TCR)
Asynchronous Reset
7.8
s
refresh interval at lower than T
CASE
85°C, 3.9s refresh interval at 85°C < T
CASE
< 95 °C
Support address and command signals parity function
Selectable BC4 or BL8 on-the fly(OTF)
Dynamic On Die Termination
Fly-by topology
Operation Temperature(T
A
): -40°C ~ +85°C
PCB Height: 0.74 inches(18.75mm)
Minimum Thickness of Golden Finger: 30 Micro-inch
RoHS compliant
Part No.
A4B04QG8BLRCSW
Max Freq
1200MHz (0.83ns@CL=17) x2
Interface
POD12
Your Ultimate Memory Solution!
Page 1 of 11
ATP A4B04QG8BLRCSW
PIN DESCRIPTION
Pin Name
A0~A17
A10/AP
A12/BC_n
BA0,BA1
BG0,BG1
RAS_n
CAS_n
WE_n
CS0_n
CK0_t
CK0_c
CKE0
C0~C2
ODT0
ACT_n
DQ0~DQ63
CB0~CB7
DQS0_t~DQS8_t
DQS0_c~DQS8_c
TDQS9_t~TDQS17_t
TDQS9_c~TDQS17_c
SCL
SDA
SA0~SA2
PARITY
VDD
VPP
VREFCA
VSS
VDDSPD
ALERT_n
RESET_n
EVENT_n
VTT
VDDQ
ZQ
NC
NF
RFU
Description
Address Inputs
Address Input/Auto precharge
Address Input/Burst chop
SDRAM Bank Address
Bank group address inputs
Row address strobe input
Column address strobe input
Write enable input
Chip Selects
Clock Inputs, positive line
Clock Inputs, negative line
Clock Enables
Chip ID
On-die termination control lines input
Command input: ACT_n indicates an ACTIVATE command.
Data Input /Output
Data check bits Input/Output
Data strobes
Data strobes, negative line
Termination Data Strobe
Termination Data Strobe, negative line
Serial clock for temperature sensor/SPD EEPROM
SPD Data Input /Output
Serial address inputs
Parity for command and address
Power supply
DRAM activating power supply
Reference voltage for control, command, and address pins.
Ground
SPD Power
Alert output
Active LOW asynchronous reset
Temperature sensor Event Output
SDRAM I/O termination supply
DRAM DQ power supply
Reference ball for ZQ calibration
No Connect
No function
Reserved for future use
Your Ultimate Memory Solution!
2590 North First Street, San Jose, CA 95131, USA. http://www.atpinc.com
Tel. (408) 732-5000 Fax (408) 732-5055
Page 2 of 11
ATP A4B04QG8BLRCSW
PIN ASSIGNMENT
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
Designation
NC
VSS
DQ4
VSS
DQ0
VSS
TDQS9_t, DQS9_t
TDQS9_c, DQS9_c
VSS
DQ6
VSS
DQ2
VSS
DQ12
VSS
DQ8
VSS
TDQS10_t, DQS10_t
TDQS10_c, DQS10_c
VSS
DQ14
VSS
DQ10
VSS
DQ20
VSS
DQ16
VSS
TDQS11_t, DQS11_t
TDQS11_c, DQS11_c
VSS
DQ22
VSS
DQ18
VSS
DQ28
VSS
DQ24
VSS
TDQS12_t, DQS12_t
TDQS12_c, DQS12_c
No.
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
Designation
NC
VREFCA
VSS
DQ5
VSS
DQ1
VSS
DQS0_c
DQS0_t
VSS
DQ7
VSS
DQ3
VSS
DQ13
VSS
DQ9
VSS
DQS1_c
DQS1_t
VSS
DQ15
VSS
DQ11
VSS
DQ21
VSS
DQ17
VSS
DQS2_c
DQS2_t
VSS
DQ23
VSS
DQ19
VSS
DQ29
VSS
DQ25
VSS
DQS3_c
No.
74
75
76
77
Designation
CK0_t
CK0_c
VDD
VTT
No.
218
219
220
221
KEY
Designation
CK1_t
CK1_c
VDD
VTT
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
EVENT_n
A0
VDD
BA0
RAS_n/A16
VDD
S0_n
VDD
CAS_n/A15
ODT0
VDD
S1_n
VDD
ODT1
VDD
C0,CS2_n,NC
VSS
DQ36
VSS
DQ32
VSS
TDQS13_t, DQS13_t
TDQS13_c, DQS13_c
VSS
DQ38
VSS
DQ34
VSS
DQ44
VSS
DQ40
VSS
TDQS14_t, DQS14_t
TDQS14_c, DQS14_c
VSS
DQ46
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
PARITY
VDD
BA1
A10/AP
VDD
RFU
WE_n /A14
VDD
NC
VDD
A13
VDD
A17
NC,C2
VDD
NC,CS3_c,C1
SA2
VSS
DQ37
VSS
DQ33
VSS
DQS4_c
DQS4_t
VSS
DQ39
VSS
DQ35
VSS
DQ45
VSS
DQ41
VSS
DQS5_c
DQS5_t
VSS
Your Ultimate Memory Solution!
2590 North First Street, San Jose, CA 95131, USA. http://www.atpinc.com
Tel. (408) 732-5000 Fax (408) 732-5055
Page 3 of 11
ATP A4B04QG8BLRCSW
No.
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
Note:
1. VPP is 2.5V DC
Designation
VSS
DQ30
VSS
DQ26
VSS
CB4
VSS
CB0
VSS
TDQS17_t, DQS17_t
TDQS17_c, DQS17_c
VSS
CB6
VSS
CB2
VSS
RESET_n
VDD
CKE0
VDD
ACT_n
BG0
VDD
A12/BC_n
A9
VDD
A8
A6
VDD
A3
A1
VDD
No.
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
Designation
DQS3_t
VSS
DQ31
VSS
DQ27
VSS
VB5
VSS
CB1
VSS
DQS8_c
DQS8_t
VSS
VB7
VSS
CB3
VSS
CKE1
VDD
RFU
VDD
BG1
ALERT_n
VDD
A11
A7
VDD
A5
A4
VDD
A2
VDD
No.
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
Designation
VSS
DQ42
VSS
DQ52
VSS
DQ48
VSS
TDQS15_t, DQS15_t
TDQS15_c, DQS15_c
VSS
DQ54
VSS
DQ50
VSS
DQ60
VSS
DQ56
VSS
TDQS16_t, DQS16_t
TDQS16_c, DQS16_c
VSS
DQ62
VSS
DQ58
VSS
SA0
SA1
SCL
VPP
VPP
RFU
No.
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
Designation
DQ47
VSS
DQ43
VSS
DQ53
VSS
DQ49
VSS
DQS6_c
DQS6_t
VSS
DQ55
VSS
DQ51
VSS
DQ61
VSS
DQ57
VSS
DQS7_c
DQS7_t
VSS
DQ63
VSS
DQ59
VSS
VDDSPD
SDA
VPP
VPP
VPP
Your Ultimate Memory Solution!
2590 North First Street, San Jose, CA 95131, USA. http://www.atpinc.com
Tel. (408) 732-5000 Fax (408) 732-5055
Page 4 of 11
ATP A4B04QG8BLRCSW
FUNCTIONAL BLOCK DIAGRAM (PART1 OF 2)
BG[0:1]
BA[0:1]
A0-A17
C[0:2]
PARITY,ACT_n
CKE0
BG[0:1]A->BG[0:1]:DDR4 SDRAMs: U0-U4
BG[0:1]B->BG[0:1]:DDR4 SDRAMs: U5-U8
BA[0:1]A->BA[0:1]:DDR4 SDRAMs: U0-U4
BA[0:1]B->BA[0:1]:DDR4 SDRAMs: U5-U8
R
E
G
I
S
T
E
R
A[0:16]A->A[0:16]:DDR4 SDRAMs: U0-U4
A[0:16]B->A[0:16]:DDR4 SDRAMs: U5-U8
C[0:2]A -> SA[0:2]: SDRAMs:U0~U4
C[0:2]B -> SA[0:2]: SDRAMs:U5~U8
PARA -> PAR, ACT_n: SDRAMs U[0:4]
PARB -> PAR, ACT_n: SDRAMs U[5:8]
CKE0A -> CKE: SDRAMs U[0:4]
CKE0B -> CKE: SDRAMs U[5:8]
ODT0A -> ODT: SDRAMs U[0:4]
ODT0B -> ODT: SDRAMs U[5:8]
CS0A_n -> CS_n: SDRAMs U[0:4]
CS0B_n -> CS_n: SDRAMs U[5:8]
Y0(_t, _c) -> CK0(_t, _c): SDRAMs U[5:8]
Y1(_t, _c) -> CK1(_t, _c): SDRAMs U[0:4]
ODT0
CS0_n
CK0
CK0
CK1
CK1
RESET
ALERT_n
QRESET:SDRAM U1~U9
ERROR_IN_n <- ALERT_n: All SDRAMs
Your Ultimate Memory Solution!
2590 North First Street, San Jose, CA 95131, USA. http://www.atpinc.com
Tel. (408) 732-5000 Fax (408) 732-5055
Page 5 of 11
FPGA/CPLD
