Integrated
Circuit
Systems, Inc.
ICS97ULP877B
1.8V Low-Power Wide-Range Frequency Clock Driver
Recommended Application:
• DDR2 Memory Modules / Zero Delay Board Fan Out
• Provides complete DDR DIMM logic solution with
ICSSSTU32864/SSTUF32864/SSTUF32866
Product Description/Features:
• Low skew, low jitter PLL clock driver
• 1 to 10 differential clock distribution (SSTL_18)
• Feedback pins for input to output synchronization
• Spread Spectrum tolerant inputs
• Auto PD when input signal is at a certain logic state
Switching Characteristics:
• Period jitter: 40ps
• Half-period jitter: 60ps
• CYCLE - CYCLE jitter 40ps
• OUTPUT - OUTPUT skew: 40ps
Pin Configuration
1
A
B
C
D
E
F
G
H
J
K
2
3
4
5
6
52-Ball BGA
Top View
A
B
C
D
E
F
G
H
J
K
1
CLKT1
CLKC1
CLKC2
CLKT2
CLK_INT
CLK_INC
AGND
AVDD
CLKT3
CLKC3
2
CLKT0
GND
GND
VDDQ
VDDQ
VDDQ
VDDQ
GND
GND
CLKC4
3
CLKC0
GND
NB
VDDQ
NB
NB
VDDQ
NB
GND
CLKT4
4
CLKC5
GND
NB
VDDQ
NB
NB
VDDQ
NB
GND
CLKT9
5
CLKT5
GND
GND
OS
VDDQ
OE
VDDQ
GND
GND
CLKC9
6
CLKT6
CLKC6
CLKC7
CLKT7
FB_INT
FB_INC
FB_OUTC
FB_OUTT
CLKT8
CLKC8
Block Diagram
CLKT0
OE
OS
AV
DD
Powerdown
Control and
Test Logic
LD* or OE
LD*, OS or OE
CLKC0
CLKT1
CLKC1
CLKT2
LD*
PLL bypass
CLKC2
CLKT3
CLKC3
CLKT4
CLKC4
CLKT5
CLKC5
CLK_INT
CLK_INC
10K-100k
PLL
GND
FB_INT
FB_INC
* The Logic Detect (LD) powers down the device when a
logic low is applied to both CLK_INT and CLK_INC.
CLKT6
CLKC6
CLKT7
CLKC7
40
VDDQ
CLKC2
CLKT2
CLK_INT
CLK_INC
VDDQ
AGND
AVDD
VDDQ
GND
CLKC1
CLKT1
CLKT0
CLKC0
VDDQ
CLKC5
CLKT5
CLKT6
CLKC6
VDDQ
31
1
30
ICS97ULP877B
10
21
11
20
CLKC7
CLKT7
VDDQ
FB_INT
FB_INC
FB_OUTC
FB_OUTT
VDDQ
OE
OS
CLKT8
CLKC8
CLKT9
CLKC9
FB_OUTT
FB_OUTC
0981B—03/15/05
CLKT3
CLKC3
CLKC4
CLKT4
VDDQ
CLKT9
CLKC9
CLKC8
CLKT8
VDDQ
40-Pin MLF
ICS97ULP877B
Pin Descriptions
Te r m i n a l
Name
AGND
AV
DD
CLK_INT
CLK_INC
FB_INT
FB_INC
FB_OUTT
FB_OUTC
OE
OS
GND
V
DDQ
CLKT[0:9]
CLKC[0:9]
NB
Analog Ground
A n a l o g p ow e r
Clock input with a (10K-100K Ohm) pulldown resistor
Complentar y clock input with a (10K-100K Ohm) pulldown resistor
Feedback clock input
Complementary feedback clock input
Feedback clock output
Complementary feedback clock output
Output Enable (Asynchronous)
Output Select (tied to GND or V
DDQ
)
Ground
Logic and output power
Clock outputs
Complementary clock outputs
No ball
Description
Electrical
Characteristics
Ground
1.8 V nominal
Differential input
Differential input
Differential input
Differential input
Differential output
Differential output
LVCMOS input
LVCMOS input
Ground
1.8V nominal
Differential outputs
Differential outputs
The PLL clock buffer,
ICS97ULP877B,
is designed for a V
DDQ
of 1.8 V, a AV
DD
of 1.8 V and differential data input and
output levels. Package options include a plastic 52-ball VFBGA and a 40-pin MLF.
ICS97ULP877B
is a zero delay buffer that distributes a differential clock input pair (CLK_INT, CLK_INC) to ten
differential pair of clock outputs (CLKT[0:9], CLKC[0:9]) and one differential pair feedback clock outputs (FB_OUTT,
FBOUTC). The clock outputs are controlled by the input clocks (CLK_INT, CLK_INC), the feedback clocks (FB_INT,
FB_INC), the LVCMOS program pins (OE, OS) and the Analog Power input (AVDD). When OE is low, the outputs (except
FB_OUTT/FB_OUTC) are disabled while the internal PLL continues to maintain its locked-in frequency. OS (Output
Select) is a program pin that must be tied to GND or V
DDQ
. When OS is high, OE will function as described above. When
OS is low, OE has no effect on CLKT7/CLKC7 (they are free running in addition to FB_OUTT/FB_OUTC). When AV
DD
is grounded, the PLL is turned off and bypassed for test purposes.
When both clock signals (CLK_INT, CLK_INC) are logic low, the device will enter a low power mode. An input logic
detection circuit on the differential inputs, independent from the input buffers, will detect the logic low level and perform
a low power state where all outputs, the feedback and the PLL are OFF. When the inputs transition from both being logic
low to being differential signals, the PLL will be turned back on, the inputs and outputs will be enabled and the PLL
will obtain phase lock between the feedback clock pair (FB_INT, FB_INC) and the input clock pair (CLK_INT, CLK_INC)
within the specified stabilization time t
STAB
.
The PLL in
ICS97ULP877B
clock driver uses the input clocks (CLK_INT, CLK_INC) and the feedback clocks (FB_INT,
FB_INC) to provide high-performance, low-skew, low-jitter output differential clocks (CLKT[0:9], CLKC[0:9]).
ICS97ULP877B
is also able to track Spread Spectrum Clocking (SSC) for reduced EMI.
ICS97ULP877B
is characterized for operation from 0°C to 70°C.
0981B—03/15/05
2
ICS97ULP877B
Function Table
Inputs
AVDD
GND
GND
GND
GND
1.8V(nom)
1.8V(nom)
1.8V(nom)
1.8V(nom)
1.8V(nom)
1.8V(nom)
OE
H
H
L
L
L
L
H
H
X
X
OS
X
X
H
L
H
L
X
X
X
X
CLK_INT
L
H
L
H
L
H
L
H
L
H
CLK_INT
H
L
H
L
H
L
H
L
L
H
CLKT
L
H
*L(Z)
*L(Z),
CLKT7
active
*L(Z)
*L(Z),
CLKT7
active
L
H
*L(Z)
CLKC
H
L
*L(Z)
*L(Z),
CLKC7
active
*L(Z)
*L(Z),
CLKC7
active
H
L
*L(Z)
Outputs
PLL
FB_OUTT
L
H
L
H
L
H
FB_OUTC
H
L
H
L
Bypassed/Off
Bypassed/Off
Bypassed/Off
Bypassed/Off
H
L
On
On
L
H
*L(Z)
Reser ved
H
L
*L(Z)
On
On
Off
*L(Z) means the outputs are disabled to a low stated meeting the I
ODL
limit.
0981B—03/15/05
3
ICS97ULP877B
Absolute Maximum Ratings
Supply Voltage (VDDQ & AVDD) . . . . . . . . .
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . .
Ambient Operating Temperature . . . . . . . . . .
Storage Temperature . . . . . . . . . . . . . . . . . . .
-0.5V to 2.5V
GND - 0.5V to V
DDQ
+ 0.5V
0°C to +70°C
-65°C to +150°C
Stresses above those listed under
Absolute Maximum Ratings
may cause permanent damage to the device. These
ratings are stress specifications only and functional operation of the device at these or any other conditions above those
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70°C; Supply Voltage AVDDQ, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
Input High Current
V
I
= V
DDQ
or GND
I
IH
(CLK_INT, CLK_INC)
Input Low Current (OE,
V
I
= V
DDQ
or GND
I
IL
OS, FB_INT, FB_INC)
Output Disabled Low
OE = L, V
ODL
= 100mV
100
I
ODL
Current
I
DD1.8
C
L
= 0pf @ 270MHz
Operating Supply
Current
I
DDLD
C
L
= 0pf
Input Clamp Voltage
V
IK
V
DDQ
= 1.7V Iin = -18mA
High-level output
I
OH
= -100 A
V
DDQ
- 0.2
V
OH
voltage
I
OH
= -9 mA
1.1
1.45
I
OL
=100 A
0.25
Low-level output voltage
V
OL
I
OL
=9 mA
C
IN
V
I
= GND or V
DDQ
2
Input Capacitance
1
C
OUT
V
OUT
= GND or V
DDQ
2
Output Capacitance
1
1
MAX
±250
±10
UNITS
µA
µA
µA
200
500
-1.2
mA
µA
V
V
V
V
V
pF
pF
0.10
0.6
3
3
Guaranteed by design, not 100% tested in production.
0981B—03/15/05
4
ICS97ULP877B
Recommended Operating Condition
(see note1)
T
A
= 0 - 70°C; Supply Voltage AVDD, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated)
PARAMETER
Supply Voltage
Low level input voltage
SYMBOL
V
DDQ
, A
VDD
V
IL
CONDITIONS
MIN
1.7
TYP
1.8
MAX
1.9
0.35 x V
DDQ
0.35 x V
DDQ
UNITS
V
V
V
V
V
V
DDQ
+ 0.3
V
DDQ
+ 0.4
V
DDQ
+ 0.4
V
DDQ
/2 + 0.10
V
V
V
V
V
mA
mA
°C
High level input voltage
DC input signal voltage
(note 2)
Differential input signal
voltage (note 3)
Output differential cross-
voltage (note 4)
Input differential cross-
voltage (note 4)
High level output current
Low level output current
Operating free-air
temperature
V
IH
V
IN
CLK_INT, CLK_INC, FB_INC,
FB_INT
OE, OS
CLK_INT, CLK_INC, FB_INC,
0.65 x V
DDQ
FB_INT
OE, OS
0.65 x V
DDQ
-0.3
DC - CLK_INT, CLK_INC,
FB_INC, FB_INT
AC - CLK_INT, CLK_INC,
FB_INC, FB_INT
0.3
0.6
V
DDQ
/2 - 0.10
V
ID
V
OX
V
IX
I
OH
I
OL
T
A
V
DDQ
/2 - 0.15 V
DD
/2 V
DDQ
2 + 0.15
-9
9
0
70
Notes:
1. Unused inputs must be held high or low to prevent them from floating.
2. DC input signal voltage specifies the allowable DC execution of differential input.
3. Differential inputs signal voltages specifies the differential voltage [VTR-VCP]
required for switching, where VTR is the true input level and VCP is the
complementary input level.
4. Differential cross-point voltage is expected to track variations of V
DDQ
and is the
voltage at which the differential signal must be crossing.
0981B—03/15/05
5
