Integrated
Circuit
Systems, Inc.
ICS9DB108
(Not recommended for new designs)
Eight Output Differential Buffer for PCI-Express
Recommended Application:
DB800 Intel Yellow Cover part with PCI-Express support.
Output Features:
•
8 - 0.7V current-mode differential output pairs
•
Supports zero delay buffer mode and fanout mode
•
Bandwidth programming available
Key Specifications:
•
Outputs cycle-cycle jitter < 50ps
•
Outputs skew: 50ps
•
+/- 300ppm frequency accuracy on output clocks
Features/Benefits:
•
Supports tight ppm accuracy clocks for Serial-ATA
•
Spread spectrum modulation tolerant, 0 to -0.5% down
spread and +/- 0.25% center spread
•
Supports undriven differential output pair in PD# and
SRC_STOP# for power management.
Pin Configuration
d
e
d s
n n
e g
m si
m de
o
c w
e e
r
t n
o
N
SRC_DIV#
VDD
GND
SRC_IN
SRC_IN#
OE_0
OE_3
DIF_0
DIF_0#
GND
VDD
DIF_1
DIF_1#
OE_1
OE_2
DIF_2
DIF_2#
GND
VDD
DIF_3
DIF_3#
BYPASS#/PLL
SCLK
SDATA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48-pin SSOP & TSSOP
0723G—12/02/08
ICS9DB108
r
fo
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDDA
GNDA
IREF
LOCK
OE_7
OE_4
DIF_7
DIF_7#
GND
VDD
DIF_6
DIF_6#
OE_6
OE_5
DIF_5
DIF_5#
GND
VDD
DIF_4
DIF_4#
HIGH_BW#
SRC_STOP#
PD#
GND
Integrated
Circuit
Systems, Inc.
ICS9DB108
(Not recommended for new designs)
Pin Description
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
PIN NAME
SRC_DIV#
VDD
GND
SRC_IN
SRC_IN#
OE_0
OE_3
DIF_0
DIF_0#
GND
VDD
DIF_1
DIF_1#
OE_1
OE_2
DIF_2
DIF_2#
GND
VDD
DIF_3
DIF_3#
BYPASS#/PLL
SCLK
SDATA
PIN TYPE
IN
PWR
PWR
IN
IN
IN
IN
OUT
OUT
PWR
PWR
OUT
OUT
IN
IN
OUT
OUT
PWR
PWR
OUT
OUT
IN
IN
I/O
DESCRIPTION
Active low Input for determining SRC output frequency SRC or
SRC/2.
0 = SRC/2, 1= SRC
Power supply, nominal 3.3V
Ground pin.
0.7 V Differential SRC TRUE input
0.7 V Differential SRC COMPLEMENTARY input
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
0.7V differential true clock outputs
0.7V differential complement clock outputs
Ground pin.
Power supply, nominal 3.3V
0.7V differential true clock outputs
0.7V differential complement clock outputs
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
0.7V differential true clock outputs
0.7V differential complement clock outputs
Ground pin.
Power supply, nominal 3.3V
0.7V differential true clock outputs
0.7V differential complement clock outputs
Input to select Bypass(fan-out) or PLL (ZDB) mode
0 = Bypass mode, 1= PLL mode
Clock pin of SMBus circuitry, 5V tolerant.
Data pin for SMBus circuitry, 5V tolerant.
0723G—12/02/08
2
Integrated
Circuit
Systems, Inc.
ICS9DB108
(Not recommended for new designs)
Pin Description (Continued)
PIN #
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
PIN NAME
GND
PD#
SRC_STOP#
HIGH_BW#
DIF_4#
DIF_4
VDD
GND
DIF_5#
DIF_5
OE_5
OE_6
DIF_6#
DIF_6
VDD
GND
DIF_7#
DIF_7
OE_4
OE_7
LOCK
PIN TYPE
PWR
IN
IN
PWR
OUT
OUT
PWR
PWR
OUT
OUT
IN
IN
OUT
OUT
PWR
PWR
OUT
OUT
IN
IN
OUT
DESCRIPTION
Ground pin.
Asynchronous active low input pin used to power down the
device. The internal clocks are disabled and the VCO and the
crystal are stopped.
Active low input to stop diff outputs.
3.3V input for selecting PLL Band Width
0 = High, 1= Low
0.7V differential complement clock outputs
0.7V differential true clock outputs
Power supply, nominal 3.3V
Ground pin.
0.7V differential complement clock outputs
0.7V differential true clock outputs
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
0.7V differential complement clock outputs
0.7V differential true clock outputs
Power supply, nominal 3.3V
Ground pin.
0.7V differential complement clock outputs
0.7V differential true clock outputs
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
Active high input for enabling outputs.
0 = tri-state outputs, 1= enable outputs
3.3V output indicating PLL Lock Status. This pin goes high
when lock is achieved.
This pin establishes the reference current for the differential
current-mode output pairs. This pin requires a fixed precision
resistor tied to ground in order to establish the appropriate
current. 475 ohms is the standard value.
Ground pin for the PLL core.
3.3V power for the PLL core.
46
47
48
IREF
GNDA
VDDA
IN
PWR
PWR
0723G—12/02/08
3
Integrated
Circuit
Systems, Inc.
ICS9DB108
(Not recommended for new designs)
General Description
ICS9DB108
follows the Intel DB400 Differential Buffer Specification. This buffer provides four SRC clocks for PCI-Express,
next generation I/O devices.
ICS9DB108
is driven by a differential input pair from a CK409/CK410 main clock generator, such
as the ICS952601 or ICS954101.
ICS9DB108
can run at speeds up to 200MHz. It provides ouputs meeting tight cycle-to-cycle
jitter (50ps) and output-to-output skew (50ps) requirements.
Block Diagram
8
OE(7:0)
SRC_IN
SRC_IN#
SPREAD
COMPATIBLE
PLL
STOP
LOGIC
8
DIF(7:0)
SRC_DIV#
HIGH_BW#
SRC_STOP#
PD#
BYPASS#/PLL
SDATA
SCLK
CONTROL
LOGIC
IREF
0723G—12/02/08
4
Integrated
Circuit
Systems, Inc.
ICS9DB108
(Not recommended for new designs)
Absolute Max
Symbol
VDD_A
VDD_In
V
IL
V
IH
Ts
Tambient
Tcase
ESD prot
Parameter
3.3V Core Supply Voltage
3.3V Logic Supply Voltage
Input Low Voltage
Input High Voltage
Storage Temperature
Ambient Operating Temp
Case Temperature
Input ESD protection
human body model
Min
Max
4.6
4.6
V
DD
+0.5V
150
70
115
Units
V
V
V
V
°
C
°C
°C
V
GND-0.5
-65
0
2000
Electrical Characteristics - Input/Supply/Common Output Parameters
T
A
= 0 - 70°C; Supply Voltage V
DD
= 3.3 V +/-5%
PARAMETER
Input High Voltage
Input Low Voltage
Input High Current
SYMBOL
V
IH
V
IL
I
IH
I
IL1
Input Low Current
I
IL2
Operating Supply Current
Powerdown Current
Input Frequency
3
Pin Inductance
1
CONDITIONS
MIN
3.3 V +/-5%
2
GND - 0.3
3.3 V +/-5%
V
IN
= V
DD
-5
V
IN
= 0 V; Inputs with no pull-up
-5
resistors
V
IN
= 0 V; Inputs with pull-up
-200
resistors
Full Active, C
L
= Full load;
all diff pairs driven
all differential pairs tri-stated
V
DD
= 3.3 V
80
TYP
MAX
UNITS NOTES
V
DD
+ 0.3
V
0.8
V
5
uA
uA
uA
250
60
12
mA
mA
mA
MHz
nH
pF
pF
MHz
MHz
1
33
10
300
5
5
ms
kHz
ns
us
ns
ns
3
1
1
1
1
1
1,2
1
1,3
1,3
1
2
I
DD3.3OP
I
DD3.3PD
F
i
L
pin
C
IN
C
OUT
100/133
166/200
220
7
5
6
Logic Inputs
1.5
Output pin capacitance
PLL Bandwidth when
PLL_BW=0
PLL Bandwidth
BW
PLL Bandwidth when
PLL_BW=1
From V
DD
Power-Up and after
1,2
T
STAB
input clock stabilization or de-
Clk Stabilization
assertion of PD# to 1st clock
Triangular Modulation
30
Modulation Frequency
DIF output enable after
Tdrive_SRC_STOP#
SRC_Stop# de-assertion
DIF output enable after
Tdrive_PD#
PD# de-assertion
Fall time of PD# and
Tfall
SRC_STOP#
Rise time of PD# and
Trise
SRC_STOP#
1
Guaranteed by design and characterization, not 100% tested in production.
2
See timing diagrams for timing requirements.
3
Time from deassertion until outputs are >200 mV
Input Capacitance
1
0723G—12/02/08
4
2
5
