DATASHEET
FOUR OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1,2,3
9DB433
General Description
The 9DB433 zero-delay buffer supports PCIe Gen3
requirements, while being backwards compatible to PCIe
Gen2 and Gen1. The 9DB433 is driven by a differential
SRC output pair from an IDT 932S421 or 932SQ420 or
equivalent main clock generator.
Features/Benefits
•
3 Selectable SMBus Addresses; Mulitple devices can
•
•
•
•
•
•
share the same SMBus Segment
OE# pins; Suitable for Express Card applications
PLL or bypass mode; PLL can dejitter incoming clock
Selectable PLL bandwidth; minimizes jitter peaking in
downstream PLL's
Spread Spectrum Compatible; tracks spreading input
clock for low EMI
SMBus Interface; unused outputs can be disabled
Supports undriven differential outputs in Power Down
mode for power management
Recommended Application
4 output PCIe Gen1,2,3 zero-delay/fanout buffer
Key Specifications
•
Output cycle-cycle jitter <50ps
•
Output to Output skew <50ps
•
Phase jitter: PCIe Gen3 <1.0ps rms
Output Features
•
•
•
•
•
4 - 0.7V current-mode differential HCSL output pairs
Supports zero delay buffer mode and fanout mode
Selectable bandwidth
50-110 MHz operation in PLL mode
5-166 MHz operation in Bypass mode
Functional Block Diagram
2
OE(6,1)#
SRC_IN
SRC_IN#
SPREAD
COMPATIBLE
PLL
M
U
X
4
STOP
LOGIC
DIF(6,5,2,1)
PD#
BYP#_LOBW_HIBW
SMBDAT
SMBCLK
CONTROL
LOGIC
IREF
IDT®
FOUR OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1,2,3
1
9DB433
REV G 08/25/15
9DB433
FOUR OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1,2,3
Pin Configuration
VDDR
SRC_IN
SRC_IN#
GND
VDD
DIF_1
DIF_1#
OE1#
DIF_2
DIF_2#
VDD
BYP#_HIBW_LOBW
SMBCLK
SMBDAT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDDA
GNDA
IREF
PD#
VDD
DIF_6
DIF_6#
OE6#
DIF_5
DIF_5#
VDD
SMB_ADR_tri
VDD
GND
Notes:
Highlighted Pins are the differences between 9DB403 and
9DB433.
Pin 12 and Pin 17 are latched on power up. Please make sure
that the power supply to the pullup/pulldown resistors ramps at
the same time as the main supply to the chip.
SMBus Address Selection and Readback
SMB_ADR_tri
Low
Mid
High
Address
DA/DB
DC/DD
D8/D9
PLL Operating Mode Readback Table
BYP#_LOBW_HIBW
Low
Mid
High
MODE
Byte0, bit 3 Byte 0 bit 1
Bypass
0
0
PLL 100M Hi BW
1
0
PLL 100M Low BW
0
1
Power Groups
Pin Number
Description
VDD
GND
1
4
SRC_IN/SRC_IN#
5,11,18, 24
4
DIF(1,2,5,6)
16
15
DIGITAL VDD/GND
28
27
Analog VDD/GND for PLL in IREF
For best results, treat pin 1 as analog VDD.
9DB433
Tri-Level Input Logic Pins
State of Pin
Low
Mid
High
Voltage
<0.8V
1.2<Vin<1.8V
Vin > 2.0V
IDT®
FOUR OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1,2,3
2
9DB433
REV G 08/25/15
9DB433
FOUR OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1,2,3
Pin Descriptions
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
PIN NAME
VDDR
SRC_IN
SRC_IN#
GND
VDD
DIF_1
DIF_1#
OE1#
DIF_2
DIF_2#
VDD
BYP#_HIBW_LOBW
SMBCLK
SMBDAT
GND
VDD
SMB_ADR_tri
VDD
DIF_5#
DIF_5
OE6#
DIF_6#
DIF_6
VDD
PD#
PIN TYPE
PWR
IN
IN
PWR
PWR
OUT
OUT
IN
OUT
OUT
PWR
IN
IN
I/O
PWR
PWR
IN
PWR
OUT
OUT
IN
OUT
OUT
PWR
IN
DESCRIPTION
3.3V power for differential input clock (receiver). This VDD should be treated as an
analog power rail and filtered appropriately.
0.7 V Differential SRC TRUE input
0.7 V Differential SRC COMPLEMENTARY input
Ground pin.
Power supply, nominal 3.3V
0.7V differential true clock output
0.7V differential Complementary clock output
Active low input for enabling DIF pair 1.
1 =disable outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential Complementary clock output
Power supply, nominal 3.3V
Tri-level input to select bypass mode, Hi BW PLL, or Lo BW PLL mode
Clock pin of SMBUS circuitry, 5V tolerant
Data pin of SMBUS circuitry, 5V tolerant
Ground pin.
Power supply, nominal 3.3V
SMBus address select bit. This is a tri-level input that decodes 1 of 3 SMBus
Addresses.
Power supply, nominal 3.3V
0.7V differential Complementary clock output
0.7V differential true clock output
Active low input for enabling DIF pair 6.
1 =disable outputs, 0 = enable outputs
0.7V differential Complementary clock output
0.7V differential true clock output
Power supply, nominal 3.3V
Asynchronous active low input pin used to power down the device. The internal
clocks are disabled and the VCO and the crystal osc. (if any) are stopped.
This pin establishes the reference for the differential current-mode output pairs. It
requires a fixed precision resistor to ground. 475ohm is the standard value for
100ohm differential impedance. Other impedances require different values. See data
sheet.
Ground pin for the PLL core.
3.3V power for the PLL core.
26
27
28
IREF
GNDA
VDDA
OUT
PWR
PWR
IDT®
FOUR OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1,2,3
3
9DB433
REV G 08/25/15
9DB433
FOUR OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1,2,3
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the 9DB433. These ratings, which are standard
values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other
conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over
the recommended operating temperature range.
PARAMETER
3.3V Core Supply Voltage
3.3V Logic Supply Voltage
Input Low Voltage
Input High Voltage
Input High Voltage
Storage Temperature
Junction Temperature
Input ESD protection
1
2
SYMBOL
VDDA/R
VDD
V
IL
V
IH
V
IHSMB
Ts
Tj
ESD prot
CONDITIONS
MIN
TYP
MAX
4.6
4.6
V
DD
+0.5V
5.5V
UNITS NOTES
V
V
V
V
V
°
GND-0.5
Except for SMBus interface
SMBus clock and data pins
-65
Human Body Model
2000
150
125
C
°C
V
1,2
1,2
1
1
1
1
1
1
Guaranteed by design and characterization, not 100% tested in production.
Operation under these conditions is neither implied nor guaranteed.
Electrical Characteristics–DIF 0.7V Current Mode Differential Outputs
T
A
= T
COM
or T
IND;
Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
Slew rate
Slew rate matching
Voltage High
Voltage Low
Max Voltage
Min Voltage
Vswing
Crossing Voltage (abs)
Crossing Voltage (var)
1
SYMBOL
Trf
∆
Trf
VHigh
VLow
Vmax
Vmin
Vswing
Vcross_abs
∆
-Vcross
CONDITIONS
Scope averaging on
Slew rate matching, Scope averaging on
Statistical measurement on single-ended signal
using oscilloscope math function. (Scope
averaging on)
Measurement on single ended signal using
absolute value. (Scope averaging off)
Scope averaging off (Differential)
Scope averaging off
Scope averaging off
MIN
1
660
-150
-300
300
250
TYP
2
800
14
806
-1
1552
375
18
MAX UNITS NOTES
4
20
850
mV
150
1150
mV
mV
mV
mV
1
1
1
1, 2
1, 5
1, 6
V/ns
%
1, 2, 3
1, 2, 4
1
550
140
Guaranteed by design and characterization, not 100% tested in production. IREF = VDD/(3xR
R
). For R
R
= 475
Ω
(1%), I
REF
= 2.32mA.
I
OH
= 6 x I
REF
and V
OH
= 0.7V @ Z
O
=50
Ω
(100
Ω
differential impedance).
Measured from differential waveform
2
3
Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around
differential 0V.
4
Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on
the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the
oscilloscope is to use for the edge rate calculations.
5
Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising
edge (i.e. Clock rising and Clock# falling).
The total variation of all Vcross measurements in any particular system. Note that this is a subset of V_cross_min/max (V_cross
absolute) allowed. The intent is to limit Vcross induced modulation by setting V_cross_delta to be smaller than V_cross absolute.
6
IDT®
FOUR OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1,2,3
4
9DB433
REV G 08/25/15
9DB433
FOUR OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1,2,3
Electrical Characteristics–Input/Supply/Common Parameters
TA = T
COM
or T
IND;
Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
Ambient Operating
Temperature
Input High Voltage
Input Low Voltage
SYMBOL
T
COM
T
IND
V
IH
V
IL
I
IN
Input Current
I
INP
F
ibyp
F
ipll
L
pin
C
IN
C
INDIF_IN
C
OUT
Clk Stabilization
Input SS Modulation
Frequency
OE# Latency
Tdrive_PD#
Tfall
Trise
SMBus Input Low Voltage
SMBus Input High Voltage
SMBus Output Low Voltage
SMBus Sink Current
Nominal Bus Voltage
SCLK/SDATA Rise Time
SCLK/SDATA Fall Time
SMBus Operating
Frequency
1
2
3
4
5
CONDITIONS
Commmercial range
Industrial range
Single-ended inputs, except SMBus, low
threshold and tri-level inputs
Single-ended inputs, except SMBus, low
threshold and tri-level inputs
Single-ended inputs, V
IN
= GND, V
IN
= VDD
Single-ended inputs
V
IN
= 0 V; Inputs with internal pull-up resistors
V
IN
= VDD; Inputs with internal pull-down resistors
V
DD
= 3.3 V, Bypass mode
V
DD
= 3.3 V, 100MHz PLL mode
Logic Inputs, except DIF_IN
DIF_IN differential clock inputs
Output pin capacitance
From V
DD
Power-Up and after input clock
stabilization or de-assertion of PD# to 1st clock
Allowable Frequency
(Triangular Modulation)
DIF start after OE# assertion
DIF stop after OE# deassertion
DIF output enable after
PD# de-assertion
Fall time of control inputs
Rise time of control inputs
MIN
0
-40
2
GND - 0.3
-5
-200
5
50
1.5
1.5
TYP
MAX
70
85
V
DD
+ 0.3
0.8
UNITS NOTES
°C
°C
V
V
uA
uA
MHz
MHz
nH
pF
pF
pF
ms
1
1
1
1
1
1
2
2
1
1
1,4
1
1,2
-0.02
5
200
166
110
7
5
2.7
6
1
Input Frequency
Pin Inductance
Capacitance
100
T
STAB
f
MODIN
30
31.5
33
kHz
1
t
LATOE#
t
DRVPD
t
F
t
R
V
ILSMB
V
IHSMB
V
OLSMB
I
PULLUP
V
DDSMB
t
RSMB
t
FSMB
f
MAXSMB
1
2
13
3
300
5
5
0.8
cycles
us
ns
ns
V
V
V
mA
V
ns
ns
kHz
1,3
1,3
1,2
1,2
1
1
1
1
1
1
1
1,5
2.1
@ I
PULLUP
@ V
OL
3V to 5V +/- 10%
(Max VIL - 0.15) to (Min VIH + 0.15)
(Min VIH + 0.15) to (Max VIL - 0.15)
Maximum SMBus operating frequency
4
2.7
V
DDSMB
0.4
5.5
1000
300
100
Guaranteed by design and characterization, not 100% tested in production.
Control input must be monotonic from 20% to 80% of input swing.
Time from deassertion until outputs are >200 mV
DIF_IN input
The differential input clock must be running for the SMBus to be active
IDT®
FOUR OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1,2,3
5
9DB433
REV G 08/25/15
