6 O/P 1.8V PCIe Gen1-2-3 ZDB/FOB
w/Zo=100ohms
9DBV0641
DATASHEET
Description
The 9DBV0641 is a member of IDT's 1.8V Very-Low-Power
(VLP) PCIe family. It has integrated output terminations
providing Zo=100ohms for direct connection to 100ohm
transmission lines. The device has 6 output enables for clock
management and 3 selectable SMBus addresses.
Features/Benefits
•
Direct connection to 100ohm transmission lines; saves 24
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•
•
•
•
•
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resistors compared to standard PCIe devices
55mW typical power consumption in PLL mode; minimal
power consumption
Outputs can optionally be supplied from any voltage
between 1.05 and 1.8V; maximum power savings
OE# pins; support DIF power management
HCSL compatible differential input; can be driven by
common clock sources
Spread Spectrum tolerant; allows reduction of EMI
Programmable Slew rate for each output; allows tuning for
various line lengths
Programmable output amplitude; allows tuning for various
application environments
Pin/software selectable PLL bandwidth and PLL Bypass;
minimize phase jitter for each application
Outputs blocked until PLL is locked; clean system start-up
Configuration can be accomplished with strapping pins;
SMBus interface not required for device control
3.3V tolerant SMBus interface works with legacy controllers
Space saving 40-pin 5x5mm VFQFPN; minimal board
space
3 selectable SMBus addresses; multiple devices can easily
share an SMBus segment
Recommended Application
1.8V PCIe Gen1-2-3 Zero Delay/Fanout Buffer (ZDB/FOB)
Output Features
•
6 - 1-200 MHz Low-Power (LP) HCSL DIF pairs
w/Zo=100
Key Specifications
•
•
•
•
DIF cycle-to-cycle jitter <50ps
DIF output-to-output skew <50ps
DIF phase jitter is PCIe Gen1-2-3 compliant
DIF
additive
phase jitter <300fs rms for SGMII
Block Diagram
vOE(5:0)#
6
CLK_IN
CLK_IN#
DIF5
SS-
Compatible
PLL
DIF4
DIF3
DIF2
CONTROL
LOGIC
DIF1
DIF0
vSADR
^vHIBW_BYPM_LOBW#
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
9DBV0641 REVISION B 09/11/14
1
©2014 Integrated Device Technology, Inc.
9DBV0641 DATASHEET
Pin Configuration
^CKPWRGD_PD#
40 39 38 37 36 35 34 33 32 31
vSADR_tri
^vHIBW_BYPM_LOBW#
FB_DNC
FB_DNC#
VDDR1.8
CLK_IN
CLK_IN#
GNDDIG
SCLK_3.3
SDATA_3.3
1
2
3
4
5
6
7
8
9
10
VDDDIG1.8
VDDIO
30
29
28
27
26
25
24
23
22
21
DIF1#
NC
NC
vOE3#
DIF3#
DIF3
VDDIO
VDDA1.8
vOE2#
DIF2#
DIF2
vOE1#
9DBV0641
Paddle is GND
11 12 13 14 15 16 17 18 19 20
vOE0#
DIF0#
DIF0
VDD1.8
VDDIO
DIF1
40-pin VFQFPN
^ prefix indicates internal Pull-Up Resistor
v prefix indicates Internal Pull-Dow n Resistor
5mm x 5mm 0.4mm pin pitch
SMBus Address Selection Table
State of SADR on first application of
CKPWRGD_PD#
SADR
0
M
1
Address
1101011
1101100
1101101
+
Read/Write bit
x
x
x
Power Management Table
DIFx
SMBus
OEx# Pin
OEx bit
True O/P Comp. O/P
0
X
X
X
Low
Low
1
Running
0
X
Low
Low
1
Running
1
0
Running
Running
1
Running
1
1
Low
Low
1. If Bypass mode is selected, the PLL will be off, and outputs will follow this table.
CKPWRGD_PD#
CLK_IN
PLL
Off
On
1
On
1
On
1
6 O/P 1.8V PCIE GEN1-2-3 ZDB/FOB W/ZO=100OHMS
2
VDD1.8
VDDIO
VDDIO
vOE5#
vOE4#
DIF5#
DIF4#
DIF5
DIF4
REVISION B 09/11/14
9DBV0641 DATASHEET
Power Connections
Pin Number
VDD
5
11
16, 31
25
12,17,26,32,
39
VDDIO
GND
41
8
41
41
Description
Input
receiver
analog
Digital Power
DIF outputs,
Logic
PLL Analog
Frequency Select Table
FSEL
Byte3 [1:0]
00
01
10
11
CLK_IN
(MHz)
100.00
50.00
125.00
Reserved
DIFx
(MHz)
CLK_IN
CLK_IN
CLK_IN
Reserved
PLL Operating Mode
HiBW_BypM_LoBW#
0
M
1
MODE
PLL Lo BW
Bypass
PLL Hi BW
Byte1 [7:6]
Readback
00
01
11
Byte1 [4:3]
Control
00
01
11
REVISION B 09/11/14
3
6 O/P 1.8V PCIE GEN1-2-3 ZDB/FOB W/ZO=100OHMS
9DBV0641 DATASHEET
Pin Descriptions
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
PIN NAME
vSADR_tri
^vHIBW_BYPM_LOBW#
FB_DNC
FB_DNC#
VDDR1.8
CLK_IN
CLK_IN#
GNDDIG
SCLK_3.3
SDATA_3.3
VDDDIG1.8
VDDIO
vOE0#
DIF0
DIF0#
VDD1.8
VDDIO
DIF1
DIF1#
NC
vOE1#
DIF2
DIF2#
vOE2#
VDDA1.8
VDDIO
DIF3
DIF3#
vOE3#
NC
VDD1.8
VDDIO
DIF4
DIF4#
vOE4#
DIF5
DIF5#
vOE5#
VDDIO
^CKPWRGD_PD#
ePAD
PIN TYPE
DESCRIPTION
LATCHED Tri-level latch to select SMBus Address. See SMBus Address Selection Table.
IN
LATCHED Trilevel input to select High BW, Bypass or Low BW mode.
IN
See PLL Operating Mode Table for Details.
True clock of differential feedback. The feedback output and feedback input are connected
DNC
internally on this pin. Do not connect anything to this pin.
Complement clock of differential feedback. The feedback output and feedback input are
DNC
connected internally on this pin. Do not connect anything to this pin.
1.8V power for differential input clock (receiver). This VDD should be treated as an Analog
PWR
power rail and filtered appropriately.
IN
True Input for differential reference clock.
IN
Complementary Input for differential reference clock.
GND
Ground pin for digital circuitry
IN
Clock pin of SMBus circuitry, 3.3V tolerant.
I/O
Data pin for SMBus circuitry, 3.3V tolerant.
PWR
1.8V digital power (dirty power)
PWR
Power supply for differential outputs
Active low input for enabling DIF pair 0. This pin has an internal pull-down.
IN
1 =disable outputs, 0 = enable outputs
OUT
Differential true clock output
OUT
Differential Complementary clock output
PWR
Power supply, nominal 1.8V
PWR
Power supply for differential outputs
OUT
Differential true clock output
OUT
Differential Complementary clock output
N/A
No Connection.
Active low input for enabling DIF pair 1. This pin has an internal pull-down.
IN
1 =disable outputs, 0 = enable outputs
OUT
Differential true clock output
OUT
Differential Complementary clock output
Active low input for enabling DIF pair 2. This pin has an internal pull-down.
IN
1 =disable outputs, 0 = enable outputs
PWR
1.8V power for the PLL core.
PWR
Power supply for differential outputs
OUT
Differential true clock output
OUT
Differential Complementary clock output
Active low input for enabling DIF pair 3. This pin has an internal pull-down.
IN
1 =disable outputs, 0 = enable outputs
N/A
No Connection.
PWR
Power supply, nominal 1.8V
PWR
Power supply for differential outputs
OUT
Differential true clock output
OUT
Differential Complementary clock output
Active low input for enabling DIF pair 4. This pin has an internal pull-down.
IN
1 =disable outputs, 0 = enable outputs
OUT
Differential true clock output
OUT
Differential Complementary clock output
Active low input for enabling DIF pair 5. This pin has an internal pull-down.
IN
1 =disable outputs, 0 = enable outputs
PWR
Power supply for differential outputs
Input notifies device to sample latched inputs and start up on first high assertion. Low enters
IN
Power Down Mode, subsequent high assertions exit Power Down Mode. This pin has internal
pull-up resistor.
GND
Connect paddle to ground.
6 O/P 1.8V PCIE GEN1-2-3 ZDB/FOB W/ZO=100OHMS
4
REVISION B 09/11/14
9DBV0641 DATASHEET
Test Loads
Low-Power HCSL Differential Output Test Load
5 inches
Rs
Zo=100W
2pF
2pF
Rs
Device
Driving LVDS
3.3V
Driving LVDS
Cc
R7a
R7b
Rs
Zo
Cc
R8a
Rs
Device
R8b
LVDS Clock
input
Driving LVDS inputs
Value
Receiver has Receiver does not
termination
have termination Note
10K ohm
140 ohm
5.6K ohm
75 ohm
0.1 uF
0.1 uF
1.2 volts
1.2 volts
Component
R7a, R7b
R8a, R8b
Cc
Vcm
REVISION B 09/11/14
5
6 O/P 1.8V PCIE GEN1-2-3 ZDB/FOB W/ZO=100OHMS
