2:4 3.3V PCIe Clock Mux
9DML0441 / 9DML0451
DATASHEET
Description
The 9DML0441 / 9DML0451 devices are 3.3V members of
IDT's Full-Featured PCIe family. They support PCIe Gen1-4
Common Clocked (CC), Separate Reference no Spread
(SRnS), and Separate Reference Independent Spread
(SRIS) architectures. The parts provide a choice of
asynchronous and glitch-free switching modes, and offer a
choice of integrated output terminations for direct connection
to 85 or 100 transmission lines. The 9DML04P1 can be
factory programmed with a user-defined power-up default
configuration.
Features
•
Direct connection to 100 (xx41) or 85 (xx51)
•
•
•
transmission lines saves up to 16 resistors
79mW typical power consumption
Spread Spectrum (SS) compatible
Factory programmed P1 device allows exact optimization
to customer requirements:
•
Control input polarity
•
Control input pull up/downs
•
Slew rate for each output
•
Differential output amplitude
•
Output impedance for each output
OE# pins for each output
HCSL-compatible differential inputs; can be driven by
common clock source
Selectable asynchronous or glitch-free switching; allows
the mux to be selected at power-up even if both inputs are
not running, then transition to glitch-free switching mode
Space saving 4 × 4 mm 24-VFQFPN
Typical Applications
Servers, ATCA, ATE, Storage, Master/Slave applications
•
•
•
•
Output Features
•
Four 1–200MHz Low-Power HCSL (LP-HCSL) DIF pairs
•
9DML0441 default Z
OUT
= 100
•
9DML0451 default Z
OUT
= 85
•
9DML04P1 factory programmable defaults
•
See
AN-891
for easy termination to other logic levels
Key Specifications
•
•
•
•
•
PCIe Gen1–4 CC compliant
PCIe Gen2–3 SRIS compliant
Output-to-output skew < 50ps
PCIe Gen4 additive phase jitter is < 0.1 ps rms
12kHz–20MHz additive phase jitter 285fs rms typical
at156.25MHz
Block Diagram
VDDR3.3 x2
^OE(3:0)#
DIF_INA#
DIF_INA
DIF_INB#
DIF_INB
vSW_MODE
^SEL_A_B#
GNDR x2
EPAD/GND
GND
4
DIF3#
DIF3
DIF2#
DIF2
DIF1#
DIF1
DIF0#
DIF0
VDD3.3
A
B
Note:
Resistors default to internal on xx41/xx51 devices. P1 devices have programmable default impedances on an output-by-output basis.
9DML0441 / 9DML0451 AUGUST 27, 2018
1
©2018 Integrated Device Technology, Inc.
9DML0441 / 9DML0451 DATASHEET
Pin Configuration
^SEL_A_B#
^OE3#
^OE2#
18 DIF2#
17 DIF2
14 DIF1#
13 DIF1
7
GNDR
8
vSW_MODE
9 10 11 12
^OE0#
DIF0#
^OE1#
DIF0
2
GNDR
DIF3#
24 23 22 21 20 19
DIF_INA 1
DIF_INA# 2
VDDR3.3 3
VDDR3.3 4
DIF_INB
5
DIF_INB# 6
9DML04xx
16 VDD3.3
Connect EPAD
15 GND
to GND
24-VFQFPN, 4 x 4 mm, 0.5mm pitch
^ prefix indicates internal pull-up resistor
v prefix indicates internal pull-down resistor
Power Management Table
OEx# Pin
0
1
DIF_IN
Running
Running
DIFx
True O/P Comp. O/P
Running
Running
Low
Low
Power Connections
Pin Number
VDD
GND
3
24
4
7
16
15
Description
Input A receiver analog
Input B receiver analog
DIF outputs
2:4 3.3V PCIE CLOCK MUX
DIF3
AUGUST 27, 2018
9DML0441 / 9DML0451 DATASHEET
Pin Descriptions
Pin# Pin Name
1 DIF_INA
2 DIF_INA#
3
4
5
6
7
VDDR3.3
VDDR3.3
DIF_INB
DIF_INB#
GNDR
Type
IN
IN
PWR
PWR
IN
IN
GND
Pin Description
HCSL Differential True input
HCSL Differential Complement Input
3.3V power for differential input clock (receiver). This VDD should be treated
as an Analog power rail and filtered appropriately.
3.3V power for differential input clock (receiver). This VDD should be treated
as an Analog power rail and filtered appropriately.
HCSL Differential True input
HCSL Differential Complement Input
Analog Ground pin for the differential input (receiver)
Switch Mode. This pin selects either asynchronous or glitch-free switching of
the mux. Use asynchronous mode if 0 or 1 of the input clocks is running.
Use glitch-free mode if both input clocks are running. This pin has an internal
pull down resistor of ~120kohms.
0 = asynchronous mode
1 = glitch-free mode
Active low input for enabling DIF pair 0. This pin has an internal pull-up
resistor.
1 =disable outputs, 0 = enable outputs
Differential true clock output
Differential Complementary clock output
Active low input for enabling DIF pair 1. This pin has an internal pull-up
resistor.
1 =disable outputs, 0 = enable outputs
Differential true clock output
Differential Complementary clock output
Ground pin.
Power supply, nominal 3.3V
Differential true clock output
Differential Complementary clock output
Active low input for enabling DIF pair 2. This pin has an internal pull-up
resistor.
1 =disable outputs, 0 = enable outputs
Differential true clock output
Differential Complementary clock output
Active low input for enabling DIF pair 3. This pin has an internal pull-up
resistor.
1 =disable outputs, 0 = enable outputs
Input to select differential input clock A or differential input clock B. This
input has an internal pull-up resistor.
0 = Input B selected, 1 = Input A selected.
Analog Ground pin for the differential input (receiver)
Connect to Ground.
8
vSW_MODE
IN
9
10
11
12
13
14
15
16
17
18
19
20
21
22
^OE0#
DIF0
DIF0#
^OE1#
DIF1
DIF1#
GND
VDD3.3
DIF2
DIF2#
^OE2#
DIF3
DIF3#
^OE3#
IN
OUT
OUT
IN
OUT
OUT
GND
PWR
OUT
OUT
IN
OUT
OUT
IN
23
24
25
^SEL_A_B#
GNDR
EPAD
IN
GND
GND
AUGUST 27, 2018
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2:4 3.3V PCIE CLOCK MUX
9DML0441 / 9DML0451 DATASHEET
Test Loads
Low-Power HCSL Differential Output Test Load
5 inches
Rs
Zo (ohms)
2pF
2pF
Terminations
Device
9DML0441
9DML0451
9DML04P1
9DML0441
9DML0451
9DML04P1
Zo (Ω)
100
100
100
85
85
85
Rs (Ω)
None needed
7.5
Prog.
N/A
None needed
Prog.
Rs
Device
Alternate Terminations
The 9DML family can easily drive LVPECL, LVDS, and CML logic. See
“AN-891 Driving LVPECL, LVDS, and CML Logic with
IDT's "Universal" Low-Power HCSL Outputs”
for details.
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the 9DML0441 / 9DML0451. These ratings, which are
standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other
conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the
recommended operating temperature range.
Parameter
Supply Voltage
Input Voltage
Input High Voltage, SMBus
Storage Temperature
Junction Temperature
Input ESD protection
1
2
3
Symbol
VDDx
V
IN
V
IHSMB
Ts
Tj
ESD prot
Conditions
Minimum
-0.5
Typical
Maximum
4.6
V
DD
+0.5
3.9
150
125
Units
V
V
V
°C
°C
V
Notes
1,2
1,3
1
1
1
1
SMBus clock and data pins
-65
Human Body Model
2500
Guaranteed by design and characterization, not 100% tested in production.
Operation under these Conditions is neither implied nor guaranteed.
Not to exceed 4.6V.
Electrical Characteristics–Clock Input Parameters
T
A
= T
AMB
, Supply Voltages per normal operation Conditions, See Test Loads for Loading Conditions
Parameter
Input Common Mode Voltage -
DIF_IN
Input Swing - DIF_IN
Input Slew Rate - DIF_IN
Input Leakage Current
Input Duty Cycle
Input Jitter - Cycle to Cycle
1
2
Symbol
V
COM
V
SWING
dv/dt
I
IN
d
tin
J
DIFIn
Conditions
Common Mode Input Voltage
Differential value
Measured differentially
V
IN
= V
DD ,
V
IN
= GND
Measurement from differential waveform
Differential Measurement
Minimum
150
300
0.4
-5
45
0
Typical
Maximum
900
8
5
55
125
Units
mV
mV
V/ns
uA
%
ps
Notes
1
1
1,2
1
1
Guaranteed by design and characterization, not 100% tested in production.
Slew rate measured through +/-75mV window centered around differential zero.
4
AUGUST 27, 2018
2:4 3.3V PCIE CLOCK MUX
9DML0441 / 9DML0451 DATASHEET
Electrical Characteristics–Current Consumption
T
A
= T
AMB
, Supply Voltages per normal operation Conditions, See Test Loads for Loading Conditions
Parameter
Operating Supply Current
Powerdown Current
1
Symbol
I
DD
I
DDPD
Conditions
VDD, All outputs active at 100MHz
VDD, all outputs disabled
Minimum
Typical
24
2
Maximum
31
3
Units
mA
mA
Notes
1
Input clock stopped.
Electrical Characteristics–Input/Supply/Common Parameters–Normal Operating
Conditions
T
A
= T
AMB
, Supply Voltages per normal operation Conditions, See Test Loads for Loading Conditions
Parameter
Symbol
Supply Voltage
VDDx
Ambient Operating Temperature
T
AMB
Input High Voltage
Input Low Voltage
V
IH
V
IL
I
IN
Input Current
I
INP
F
ibyp
L
pin
C
IN
Capacitance
C
INDIF_IN
C
OUT
Clk Stabilization
T
STAB
Logic Inputs, except DIF_IN
DIF_IN differential clock inputs
Output pin capacitance
From V
DD
Power-Up and after input clock stabilization
or de-assertion of PD# to 1st clock
Allowable Frequency for PCIe Applications
(Triangular Modulation)
Allowable Frequency for non-PCIe Applications
(Triangular Modulation)
DIF start after OE# assertion
DIF stop after OE# deassertion
Fall time of single-ended control inputs
Rise time of single-ended control inputs
0.74
30
0
1
2
31.5
1.5
1.5
Conditions
Supply voltage for core and analog
Industrial range
Single-ended inputs, except SMBus
Single-ended inputs, except SMBus
Single-ended inputs, V
IN
= GND, V
IN
= VDD
Single-ended inputs
V
IN
= 0 V; Inputs with internal pull-up resistors
V
IN
= VDD; Inputs with internal pull-down resistors
Input Frequency
Pin Inductance
1
200
7
5
2.7
6
1
33
66
3
5
5
MHz
nH
pF
pF
pF
ms
kHz
kHz
clocks
ns
ns
1,3
2
2
2
1
1
1
1
1,2
Minimum
3.135
-40
0.75 V
DD
-0.3
-5
-50
Typical
3.3
25
Maximum
3.465
85
V
DD
+ 0.3
0.25 V
DD
5
50
Units
V
°C
V
V
uA
uA
Notes
Input SS Modulation Frequency
f
MODINPCIe
PCIe
Input SS Modulation Frequency
f
MODIN
non-PCIe
OE# Latency
Tfall
Trise
1
2
3
t
LATOE#
t
F
t
R
Guaranteed by design and characterization, not 100% tested in production.
Control input must be monotonic from 20% to 80% of input swing.
Time from deassertion until outputs are > 200 mV.
AUGUST 27, 2018
5
2:4 3.3V PCIE CLOCK MUX
