DATASHEET
Programmable FTG for Differential P4
TM
CPU, PCI-Express & SATA
Clocks
Description
ICS9FG107
is a Frequency Timing Generator that provides 7
differential output pairs that are compliant to the Intel CK409/CK410
specification. It provides support for PCI-Express, next generation I/
O, and SATA. The part synthesizes several output frequencies from
either a 14.31818 Mhz crystal or a 25 MHz crystal. The device can
also be driven by a reference input clock instead of a crystal. It
provides outputs with cycle-to-cycle jitter of less than 85 ps and
output-to-output skew of less than 85 ps.
ICS9FG107
also provides a copy of the reference clock and 333
MHz PCI output clocks. Frequency selection can be accomplished
via strap pins or SMBus control.
ICS9FG107
Features/Benefits
•
•
•
•
•
•
•
•
Generates common CPU/PCI Express frequencies from
14.318 MHz or 25 MHz
Crystal or reference input
7 - 0.7V current-mode differential output pairs
3 - 33MHz PCI outputs
1 - REFOUT
Supports Serial-ATA at 100 MHz
Two spread spectrum modes: 0 to -0.5 downspread and
+/-0.25% centerspread
Unused inputs may be disabled in either driven or Hi-Z
state for power management.
Key Specifications
•
•
•
Output cycle-to-cycle jitter for DIF outputs < 50 ps (<85ps
@ 266 MHz)
Output to output skew for DIF outputs < 85 ps
+/-300 ppm frequency accuracy on output clocks
•
•
48-pin SSOP/TSSOP package
Available in RoHS compliant packaging
Funtional Block Diagram
XIN/CLKIN
X2
REFOUT
PCICLK (1:0)
SCLK
SDATA
DIF_STOP#
SEL14M_25M#
SPREAD
DWNSPRD#
OE (6:0)
FS (2:0)
I REF
Control
Logic
Programmable
Spread
PLL1
Programmable
Frequency
Dividers
PCICLK_F
DIF (6:0)
DIF# (6:0)
IDT
TM
/ICS
TM
Programmable FTG for Differential P4
TM
CPU, PCI-Express & SATA Clocks
ICS9FG107
REV F 08/21/07
1
ICS9FG107
Programmable FTG for Differential P4
TM
CPU, PCI-Express & SATA Clocks
Pin Configuration
XIN/CLKIN
X2
VDD
GND
FS2/REFOUT*
GND
FS0/PCICLK_F*
PCICLK0
PCICLK1
VDD
OE_6**
DIF_6
DIF_6#
VDD
GND
OE_5**
DIF_5
DIF_5#
VDD
DIF_4
DIF_4#
OE_4*
SDATA
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDDA
GNDA
IREF
DWNSPRD#*
FS1**
OE_0*
DIF_0
DIF_0#
VDD
DIF_1
DIF_1#
OE_1**
VDD
GND
OE_2**
DIF_2
DIF_2#
VDD
DIF_3
DIF_3#
OE_3*
SEL14M_25M#**
SPREAD*
DIF_STOP#
Functionality Table
SEL14M_25M#
FS2 FS1 FS0 OUTPUT(MHz)
(FS3)
0
0
0
0
100.00
0
0
0
1
125.00
0
0
1
0
133.33
0
0
1
1
166.67
0
1
0
0
200.00
0
1
0
1
266.66
0
1
1
0
333.33
0
1
1
1
400.00
1
0
0
0
100.00
1
0
0
1
125.00
1
0
1
0
133.33
1
0
1
1
166.67
1
1
0
0
200.00
1
1
0
1
266.66
1
1
1
0
333.33
1
1
1
1
400.00
Notes:
Pins preceeded by * have 120 Kohm pull UP resistors
Pins preceeded by ** have 120 Kohm pull DOWN resistors
FS(2:0) and SEL14M_25M# are latched inputs
Power Groups
Pin Number
VDD
GND
3
4
10
6
14,19,31,36,40
15,35
N/A
47
48
47
Description
REFOUT, Digital Inputs, SMBus
PCI Outputs
DIF Outputs
IREF
Analog VDD & GND for PLL Core
IDT
TM
/ICS
TM
Programmable FTG for Differential P4
TM
CPU, PCI-Express & SATA Clocks
ICS9FG107
ICS9FG107
REV F 08/21/07
2
ICS9FG107
Programmable FTG for Differential P4
TM
CPU, PCI-Express & SATA Clocks
Pin Description
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
PIN NAME
XIN/CLKIN
X2
VDD
GND
FS2/REFOUT*
GND
FS0/PCICLK_F*
PCICLK0
PCICLK1
VDD
OE_6**
DIF_6
DIF_6#
VDD
GND
OE_5**
DIF_5
DIF_5#
VDD
DIF_4
DIF_4#
OE_4*
SDATA
SCLK
PIN TYPE
IN
OUT
PWR
PWR
I/O
PWR
I/O
OUT
OUT
PWR
IN
OUT
OUT
PWR
PWR
IN
OUT
OUT
PWR
OUT
OUT
IN
I/O
IN
DESCRIPTION
Crystal input or Reference Clock input
Crystal output, Nominally 14.318MHz
Power supply, nominal 3.3V
Ground pin.
Frequency select latch input pin / Reference clock output
Ground pin.
Frequency select latch input pin / 3.3V PCI free running clock output.
PCI clock output.
PCI clock output.
Power supply, nominal 3.3V
Active high input for enabling output 6.
0 = tri-state outputs, 1= enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Power supply, nominal 3.3V
Ground pin.
Active high input for enabling output 5.
0 = tri-state outputs, 1= enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Power supply, nominal 3.3V
0.7V differential true clock output
0.7V differential complement clock output
Active high input for enabling output 4.
0 = tri-state outputs, 1= enable outputs
Data pin for SMBus circuitry, 3.3V tolerant.
Clock pin of SMBus circuitry, 5V tolerant.
IDT
TM
/ICS
TM
Programmable FTG for Differential P4
TM
CPU, PCI-Express & SATA Clocks
ICS9FG107
REV F 08/21/07
3
ICS9FG107
Programmable FTG for Differential P4
TM
CPU, PCI-Express & SATA Clocks
Pin Description (Continued)
PIN #
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
PIN NAME
DIF_STOP#
SPREAD*
SEL14M_25M#**
OE_3*
DIF_3#
DIF_3
VDD
DIF_2#
DIF_2
OE_2**
GND
VDD
OE_1**
DIF_1#
DIF_1
VDD
DIF_0#
DIF_0
OE_0*
FS1**
DWNSPRD#*
PIN TYPE
IN
IN
IN
IN
OUT
OUT
PWR
OUT
OUT
IN
PWR
PWR
IN
OUT
OUT
PWR
OUT
OUT
IN
IN
IN
DESCRIPTION
Active low input to stop differential output clocks.
Asynchronous, active high input, with internal 120Kohm pull-up
resistor, to enable spread spectrum functionality.
Select 14.31818 MHz or 25 Mhz input frequency. 1 = 14.31818 MHz,
0 = 25 MHz
Active high input for enabling output 3.
0 = tri-state outputs, 1= enable outputs
0.7V differential complement clock output
0.7V differential true clock output
Power supply, nominal 3.3V
0.7V differential complement clock output
0.7V differential true clock output
Active high input for enabling output 2.
0 = tri-state outputs, 1= enable outputs
Ground pin.
Power supply, nominal 3.3V
Active high input for enabling output 1.
0 = tri-state outputs, 1= enable outputs
0.7V differential complement clock output
0.7V differential true clock output
Power supply, nominal 3.3V
0.7V differential complement clock output
0.7V differential true clock output
Active high input for enabling output 0.
0 = tri-state outputs, 1= enable outputs
3.3V Frequency select latched input pin.
3.3V input that selects spread mode. This input is not latched at
power up.
0 = Down Spread, 1 = Center Spread
This pin establishes the reference current for the differential current-
mode output pairs. This pin requires a fixed precision resistor tied to
ground in order to establish the appropriate current. 475 ohms is the
standard value.
Ground pin for the PLL core.
3.3V power for the PLL core.
46
47
48
IREF
GNDA
VDDA
OUT
PWR
PWR
Pins preceeded by * have 120 Kohm pull UP resistors
Pins preceeded by ** have 120 Kohm pull DOWN resistors
IDT
TM
/ICS
TM
Programmable FTG for Differential P4
TM
CPU, PCI-Express & SATA Clocks
ICS9FG107
REV F 08/21/07
4
ICS9FG107
Programmable FTG for Differential P4
TM
CPU, PCI-Express & SATA Clocks
General SMBus serial interface information for the ICS9FG107
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address DC
(H)
ICS clock will
acknowledge
Controller (host) sends the begining byte location = N
ICS clock will
acknowledge
Controller (host) sends the data byte count = X
ICS clock will
acknowledge
Controller (host) starts sending
Byte N through
Byte N + X -1
(see Note 2)
• ICS clock will
acknowledge
each byte
one at a time
• Controller (host) sends a Stop bit
•
•
•
•
•
•
•
•
How to Read:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Controller (host) will send start bit.
Controller (host) sends the write address DC
(H)
ICS clock will
acknowledge
Controller (host) sends the begining byte
location = N
ICS clock will
acknowledge
Controller (host) will send a separate start bit.
Controller (host) sends the read address DD
(H)
ICS clock will
acknowledge
ICS clock will send the data byte count = X
ICS clock sends
Byte N + X -1
ICS clock sends
Byte 0 through byte X (if X
(H)
was written to byte 8)
.
Controller (host) will need to acknowledge each byte
Controllor (host) will send a not acknowledge bit
Controller (host) will send a stop bit
Index Block Write Operation
Controlle r (Host)
starT bit
T
Slave Address DC
(H )
W Rite
WR
Beginning Byte = N
ACK
Data Byte Count = X
ACK
Beginning Byte N
ACK
X Byte
ICS (Sla ve /Re ce ive r)
Index Block Read Operation
Controlle r (Host)
T
starT bit
Slave Address DC
(H )
WR
W Rite
Beginning Byte = N
ACK
RT
Repeat starT
Slave Address DD
(H )
RD
ReaD
ACK
Data Byte Count = X
ACK
Beginning Byte N
ACK
X Byte
ICS (Sla ve /Re ce ive r)
ACK
ACK
Byte N + X - 1
ACK
P
stoP bit
Byte N + X - 1
N
P
Not acknowledge
stoP bit
IDT
TM
/ICS
TM
Programmable FTG for Differential P4
TM
CPU, PCI-Express & SATA Clocks
ICS9FG107
REV F 08/21/07
5
