DATASHEET
FREQUENCY GENERATOR FOR CPU, QPI, FBD, PCIE GEN1/2 & SATA
ICS9FG108E
Description
The ICS9FG108E is a Frequency Generator that provides 8
differential HCSL output pairs. It can be used to drive PCe
Gen1/2, SATA and USB3.0 devices. The part can use
either a 14.31818 Mhz or 25 MHz crystal. The
ICS9FG108E can also be driven by a reference input clock
instead of a crystal. It provides outputs with cycle-to-cycle
jitter of less than 50 ps and output-to-output skew of less
than 65 ps.
Features/Benefits
•
Generates common frequencies from 14.318MHz or
•
•
•
•
•
•
•
25MHz
Crystal or reference input
8 - 0.7V current-mode HCSL output pairs
Supports Serial-ATA at 100MHz
Two spread spectrum modes: -0.5% down spread and
+/-0.25% center spread; Lower EMI
31.5KHz spread modulation rate; passes USB3
compliance testing
Unused outputs may be disabled in either driven or Hi-Z
state for power manangement
I-temp version available; supports embedded
applications
Recommended Application
Frequency Generator for CPU, PCIe Gen1/2, SATA and
USB3.0
Output Features
•
8 - HCSL differential outputs
•
1 - 3.3V REF output (either 14.318M or 25M depending
on XTAL)
Key Specifications
•
•
•
•
•
Cycle to cycle jitter: < 50ps
Phase jitter: PCIe Gen1/2 <3ps rms
Output to output skew <65ps
+/-300 ppm frequency accuracy on output clocks
+/-50ppm on all output frequencies with Spread Off
Block Diagram
XIN/CLKIN
X2
OE(7:0)
OSC
REFOUT
PROGRAMMABLE
SPREAD PLL
STOP
LOGIC
8
DIF(7:0)
SPREAD
SEL14M_25M#
DIF_STOP#
FS(2:0)
SDATA
SCLK
CONTROL
LOGIC
IREF
IDT®
FREQUENCY GENERATOR FOR CPU, QPI, FBD, PCIE GEN1/2 & SATA
1
ICS9FG108E
REV C 102912
ICS9FG108E
FREQUENCY GENERATOR FOR CPU, QPI, FBD, PCIE GEN1/2 & SATA
Pin Configuration
XIN/CLKIN
X2
VDD
GND
REFOUT
vFS2
vOE_7
DIF_7
DIF_7#
VDD
DIF_6
DIF_6#
^OE_6
VDD
GND
^OE_5
DIF_5
DIF_5#
VDD
DIF_4
DIF_4#
vOE_4
SDATA
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
VDDA
GNDA
IREF
vFS0
vFS1
vOE_0
DIF_0
DIF_0#
VDD
DIF_1
DIF_1#
^OE_1
VDD
GND
^OE_2
DIF_2
DIF_2#
VDD
DIF_3
DIF_3#
vOE_3
^SEL14M_25M#
vSPREAD
DIF_STOP#
^ indicates internal 120K pull up
v indicates internal 120K pull down
Power Groups
Pin Number
VDD
GND
3
4
10,14,19,31,36,40
15,35
N/A
47
48
47
Description
REFOUT, Digital Inputs, SMBus
DIF Outputs
IREF
Analog VDD & GND for PLL Core
Frequency Select Table
SEL14M_25M#
FS2 FS1 FS0 OUTPUT(MHz)
(FS3)
0
0
0
0
100.00
0
0
0
1
125.00
0
0
1
0
133.33
0
0
1
1
166.67
0
1
0
0
200.00
0
1
0
1
266.66
0
1
1
0
333.33
0
1
1
1
400.00
1
0
0
0
100.00
1
0
0
1
125.00
1
0
1
0
133.33
1
0
1
1
166.67
1
1
0
0
200.00
1
1
0
1
266.66
1
1
1
0
333.33
1
1
1
1
400.00
IDT®
FREQUENCY GENERATOR FOR CPU, QPI, FBD, PCIE GEN1/2 & SATA
2
ICS9FG108E
REV C 102912
9FG108E
ICS9FG108E
FREQUENCY GENERATOR FOR CPU, QPI, FBD, PCIE GEN1/2 & SATA
Pin Descriptions
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
PIN NAME
XIN/CLKIN
X2
VDD
GND
REFOUT
vFS2
vOE_7
DIF_7
DIF_7#
VDD
DIF_6
DIF_6#
^OE_6
VDD
GND
^OE_5
DIF_5
DIF_5#
VDD
DIF_4
DIF_4#
vOE_4
SDATA
SCLK
PIN TYPE
IN
OUT
PWR
PWR
OUT
IN
IN
OUT
OUT
PWR
OUT
OUT
IN
PWR
PWR
IN
OUT
OUT
PWR
OUT
OUT
IN
I/O
IN
DESCRIPTION
Crystal input or Reference Clock input
Crystal output, Nominally 14.318MHz
Power supply, nominal 3.3V
Ground pin.
Reference Clock output
Frequency select pin. This pin has an internal 120k pull down resistor
Active high input for enabling output 7. This pin has a 120kohm pull down.
0 = tri-state outputs, 1= enable outputs
0.7V differential true clock output
0.7V differential Complementary clock output
Power supply, nominal 3.3V
0.7V differential true clock output
0.7V differential Complementary clock output
Active high input for enabling output 6. This pin has an internal 120kohm pull up.
0 = tri-state outputs, 1= enable outputs
Power supply, nominal 3.3V
Ground pin.
Active high input for enabling output 5. This pin has an internal 120kohm pull up.
0 = tri-state outputs, 1= enable outputs
0.7V differential true clock output
0.7V differential Complementary clock output
Power supply, nominal 3.3V
0.7V differential true clock output
0.7V differential Complementary clock output
Active high input for enabling output 4. This pin as an internal 120kohm pull down.
0 = tri-state outputs, 1= enable outputs
Data pin for SMBus circuitry, 3.3V tolerant.
Clock pin of SMBus circuitry, 5V tolerant.
Note:
^ indicates internal 120K pull up
v indicates internal 120K pull down
IDT®
FREQUENCY GENERATOR FOR CPU, QPI, FBD, PCIE GEN1/2 & SATA
3
ICS9FG108E
REV C 102912
ICS9FG108E
FREQUENCY GENERATOR FOR CPU, QPI, FBD, PCIE GEN1/2 & SATA
Pin Descriptions (cont.)
PIN #
25
26
27
PIN NAME
DIF_STOP#
vSPREAD
^SEL14M_25M#
PIN TYPE
IN
IN
IN
DESCRIPTION
Active low input to stop differential output clocks.
Asynchronous, active high input to enable spread spectrum functionality. This pin has
a 120Kohm pull down resistor.
Select 14.31818 MHz or 25 Mhz input frequency. This pin has an internal 120kohm
pull up resistor.
1 = 14.31818 MHz, 0 = 25 MHz
Active high input for enabling output 3. This pin has an internal 120kohm pull down
resistor.
0 = tri-state outputs, 1= enable outputs
0.7V differential Complementary clock output
0.7V differential true clock output
Power supply, nominal 3.3V
0.7V differential Complementary clock output
0.7V differential true clock output
Active high input for enabling output 2. This pin has in internal 120kohm pull up
resistor.
0 = tri-state outputs, 1= enable outputs
Ground pin.
Power supply, nominal 3.3V
Active high input for enabling output 1. This pin has an internal 120kohm pull up
resistor.
0 = tri-state outputs, 1= enable outputs
0.7V differential Complementary clock output
0.7V differential true clock output
Power supply, nominal 3.3V
0.7V differential Complementary clock output
0.7V differential true clock output
Active high input for enabling output 0. This pin has an internal 120kohm pull down
resistor.
0 = tri-state outputs, 1= enable outputs
3.3V Frequency select latched input pin with internal 120kohm pull down resistor.
3.3V Frequency select latched input pin with internal 120kohm pull down resistor.
This pin establishes the reference current for the differential current-mode output pairs.
This pin requires a fixed precision resistor tied to ground in order to establish the
appropriate current. 475 ohms is the standard value.
Ground pin for the PLL core.
3.3V power for the PLL core.
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
Note:
vOE_3
DIF_3#
DIF_3
VDD
DIF_2#
DIF_2
^OE_2
GND
VDD
^OE_1
DIF_1#
DIF_1
VDD
DIF_0#
DIF_0
vOE_0
vFS1
vFS0
IREF
GNDA
VDDA
IN
OUT
OUT
PWR
OUT
OUT
IN
PWR
PWR
IN
OUT
OUT
PWR
OUT
OUT
IN
IN
IN
OUT
PWR
PWR
^ indicates internal 120K pull up
v indicates internal 120K pull down
IDT®
FREQUENCY GENERATOR FOR CPU, QPI, FBD, PCIE GEN1/2 & SATA
4
ICS9FG108E
REV C 102912
ICS9FG108E
FREQUENCY GENERATOR FOR CPU, QPI, FBD, PCIE GEN1/2 & SATA
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS9FG108E. These ratings, which are
standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any
other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over
the recommended operating temperature range.
Symbol
VDD_A
VDD
Ts
Tambient
Tambient
Tcase
ESD prot
Parameter
3.3V Core Supply Voltage
3.3V Logic Supply Voltage
Storage Temperature
Ambient Operating Temp•(Commerical Grade)
Ambient Operating Temp•(Industrial Grade)
Case Temperature
Input ESD protection•human body model
Min
Max
4.6
4.6
150
+70
+85
115
Units
V
V
°
C
°C
°C
°C
V
-65
0
-40
2000
Electrical Characteristics–REF-14.318/25 MHz
T
A
= T
A M B IENT
; V
DD
= 3.3 V +/-5%;R
S
=33
Ω,
C
L
= 5 pF (unless otherwise specified)
PARAMETER
SYMBOL
CONDITIONS
MIN
Output High Voltage
V
OH
I
OH
= -1 mA
2.4
I
OL
= 1 mA
Output Low Voltage
V
OL
Rise
Fall Time
Duty Cycle
Jitter
Jitter
1
2
TYP
MAX
0.4
UNITS Notes
V
1
V
1
ns
ns
%
ps
ps
1
1
1
1
1
t
r1
t
f1
d
t1
t
jcyc-cycCOM
t
jcyc-cycIND
V
OL
= 0.4 V, V
OH
= 2.4 V
V
OH
= 2.4 V, V
OL
= 0.4 V
V
T
= 1.5 V
VT = 1.5 V (commercial)
VT = 1.5 V (industrial)
1
1
45
1.4
1.4
53
87
87
2.5
2.5
55
200
250
Guaranteed by design and characterization, not 100% tested in production.
Trim capacitors must be used to tune the REF to the exact Crystal Frequency.
Electrical Characteristics–Differential Phase Jitter Parameters
T
A
= Commercial and Industrial, Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
Symbol
t
jphasePLL
t
jphaseLo
t
jphaseHigh
Jitter, Phase
t
jphQPI
t
jphFBD3.2G
t
jphFBD4.8G
1
2
3
Conditions
PCIe Gen 1
PCIe Gen1/2
10kHz < f < 1.5MHz
PCIe Gen1/2
1.5MHz < f < Nyquist (50MHz)
QPI 133MHz 4.8G/6.4Gb,12UI
FBD specs
(11 to 33MHz)
FBD specs
Min
Typ
25.2
0.8
1.8
0.2
1.4
1.1
Max
86
3
3.1
0.5
3
2.5
Units Notes
ps (p-p) 1,2
ps
1,2
(RMS)
ps
1,2
(RMS)
ps
1,3
(RMS)
ps
1
(RMS)
ps
1
Guaranteed by design and characterization, not 100% tested in production.
See http://www.pcisig.com for complete specs
First number is 4.8G link speed, second number is 6.4G link speed. From Intel Clock Jit tool
IDT®
FREQUENCY GENERATOR FOR CPU, QPI, FBD, PCIE GEN1/2 & SATA
5
ICS9FG108E
REV C 102912
