DATASHEET
Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, &
FBD
Description
The
ICS9FG1201H
follows the Intel DB1200G Rev 1.0 Differential
Buffer Specification. This buffer provides 12 output clocks for CPU
Host Bus, PCI-Express, or Fully Buffered DIMM applications. The
outputs are configured with two groups. Both groups (DIF 9:0) and
(DIF 11:10) can be equal to or have a gear ratio to the input clock. A
differential CPU clock from a CK410B or CK410B+ main clock
generator, such as the ICS932S421, drives the ICS9FG1201. The
ICS9FG1201H
can provide outputs up to 400MHz
ICS9FG1201H
Features/Benefits
•
•
•
•
•
•
•
•
Drives 2 channels of 4 FBDIMMs (total of 8 FBDIMMs)
Power up default is all outputs in 1:1 mode
DIF_(9:0) can be “gear-shifted” from the input CPU Host
Clock
DIF_(11:10) can be “gear-shifted” from the input CPU Host
Clock
Spread spectrum compatible
Supports output clock frequencies up to 400 MHz
8 Selectable SMBus addresses
SMBus address determines PLL or Bypass mode
Key Specifications
•
•
•
DIF output cycle-to-cycle jitter < 50ps
DIF output-to-output skew < 50ps within a group
DIF output-to-output skew < 100ps across all outputs
•
•
56-pin SSOP/TSSOP package
RoHS compliant packaging
Functional Block Diagram
OE#
SPREAD
COMPATIBLE
PLL
GEAR
SHIFT
LOGIC
STOP
LOGIC
2
DIF(11:10)
OE(9:0)#
10
CLK_IN
CLK_IN#
SPREAD
COMPATIBLE
PLL
GEAR
SHIFT
LOGIC
STOP
LOGIC
10
DIF(9:0)
HIGH_BW#
FS_A_410
VTT_PWRGD#/PD
SMB_A0
SMB_A1
SMB_A2_PLLBYP#
SMBDAT
SMBCLK
CONTROL
LOGIC
IREF
IDT
TM
/ICS
TM
Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD
1371F — 09/23/09
1
ICS9FG1201H
Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD
Pin Configuration
HIGH_BW#
CLK_IN
CLK_IN#
SMB_A0
OE0#
DIF_0
DIF_0#
OE1#
DIF_1
DIF_1#
VDD
GND
DIF_2
DIF_2#
OE2#
DIF_3
DIF_3#
OE3#
DIF_4
DIF_4#
OE4#
VDD
GND
DIF_5
DIF_5#
OE5#
SMB_A1
SMBDAT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
VDDA
GNDA
IREF
OE10_11#
DIF_11
DIF_11#
VDD
GND
DIF_10
DIF_10#
FS_A_410
VTT_PWRGD#/PD
OE9#
DIF_9
DIF_9#
OE8#
DIF_8
DIF_8#
VDD
GND
DIF_7
DIF_7#
OE7#
DIF_6
DIF_6#
OE6#
SMB_A2_PLLBYP#
SMBCLK
56-pin SSOP & TSSOP
Functionality Table
DIF_(9:0) Output DIF_(11:10) Output
MHz
MHz
1
100.00
100.00
1
133.33
133.33
1
166.66
166.66
1
RESERVED
0
200.00
200.00
200.00
0
266.66
266.66
266.66
0
333.33
333.33
333.33
0
400.00
400.00
400.00
1. FS_A_410 is a low-threshold input. Please see the V
IL_FS
and V
IH_FS
specifications in the Input/Supply/Common Output Parameters Table for correct values.
FS_A_410
1
CLK_IN (CPU FSB)
MHz
100.00
133.33
166.66
IDT
TM
/ICS
TM
Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD
ICS9FG1201H
1371F — 09/23/09
2
ICS9FG1201H
Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD
Power Groups
Pin Number
VDD
GND
56
55
11,22,38,50 12,23,37,49
Description
Main PLL, Analog
DIF clocks
Pin Description
Pin # Pin Name
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
HIGH_BW#
CLK_IN
CLK_IN#
SMB_A0
OE0#
DIF_0
DIF_0#
OE1#
DIF_1
DIF_1#
VDD
GND
DIF_2
DIF_2#
OE2#
DIF_3
DIF_3#
OE3#
DIF_4
DIF_4#
OE4#
VDD
GND
DIF_5
DIF_5#
OE5#
SMB_A1
SMBDAT
Type
IN
IN
IN
IN
IN
OUT
OUT
IN
OUT
OUT
PWR
PWR
OUT
OUT
IN
OUT
OUT
IN
OUT
OUT
IN
PWR
PWR
OUT
OUT
IN
IN
I/O
Pin Description
3.3V input for selecting PLL Band Width
0 = High, 1= Low
Input for reference clock.
"Complementary" reference clock input.
SMBus address bit 0 (LSB)
Active low input for enabling DIF pair 0.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Active low input for enabling DIF pair 1.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Power supply, nominal 3.3V
Ground pin.
0.7V differential true clock output
0.7V differential complement clock output
Active low input for enabling DIF pair 2.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Active low input for enabling DIF pair 3.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Active low input for enabling DIF pair 4
1 = tri-state outputs, 0 = enable outputs
Power supply, nominal 3.3V
Ground pin.
0.7V differential true clock output
0.7V differential complement clock output
Active low input for enabling DIF pair 5.
1 = tri-state outputs, 0 = enable outputs
SMBus address bit 1
Data pin of SMBUS circuitry, 5V tolerant
IDT
TM
/ICS
TM
Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD
1371F — 09/23/09
3
ICS9FG1201H
Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD
Pin Description (continued)
Pin # Pin Name
29
SMBCLK
30
SMB_A2_PLLBYP#
Type
IN
IN
Pin Description
Clock pin of SMBUS circuitry, 5V tolerant
SMBus address bit 2. When Low, the part operates as a fanout buffer
with the PLL bypassed. When High, the part operates as a zero-delay
buffer (ZDB) with the PLL operating.
0 = fanout mode (PLL bypassed), 1 = ZDB mode (PLL used)
Active low input for enabling DIF pair 6.
1 = tri-state outputs, 0 = enable outputs
0.7V differential complement clock output
0.7V differential true clock output
Active low input for enabling DIF pair 7.
1 = tri-state outputs, 0 = enable outputs
0.7V differential complement clock output
0.7V differential true clock output
Ground pin.
Power supply, nominal 3.3V
0.7V differential complement clock output
0.7V differential true clock output
Active low input for enabling DIF pair 8.
1 = tri-state outputs, 0 = enable outputs
0.7V differential complement clock output
0.7V differential true clock output
Active low input for enabling DIF pair 9.
1 = tri-state outputs, 0 = enable outputs
Vtt_PwrGd# is an active low input used to determine when latched
inputs are ready to be sampled. PD is an asynchronous active high
input pin used to put the device into a low power state. The internal
clocks, PLLs and the crystal oscillator are stopped.
3.3V tolerant low threshold input for CPU frequency selection. This
pin requires CK410 FSA. Refer to input electrical characteristics for
Vil_FS and Vih_FS threshold values.
0.7V differential complement clock output
0.7V differential true clock output
Ground pin.
Power supply, nominal 3.3V
0.7V differential complement clock output
0.7V differential true clock output
Active low input for enabling output pairs 10 and 11.
1 = tri-state outputs, 0 = enable outputs
This pin establishes the reference current for the differential current-
mode output pairs. This pin requires a fixed precision resistor tied to
ground in order to establish the appropriate current. 475 ohms is the
standard value.
Ground pin for the PLL core.
3.3V power for the PLL core.
31
32
33
34
35
36
37
38
39
40
41
42
43
44
OE6#
DIF_6#
DIF_6
OE7#
DIF_7#
DIF_7
GND
VDD
DIF_8#
DIF_8
OE8#
DIF_9#
DIF_9
OE9#
IN
OUT
OUT
IN
OUT
OUT
PWR
PWR
OUT
OUT
IN
OUT
OUT
IN
45
VTT_PWRGD#/PD
IN
46
47
48
49
50
51
52
53
FS_A_410
DIF_10#
DIF_10
GND
VDD
DIF_11#
DIF_11
OE10_11#
IN
OUT
OUT
PWR
PWR
OUT
OUT
IN
54
55
56
IREF
GNDA
VDDA
OUT
PWR
PWR
IDT
TM
/ICS
TM
Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD
1371F — 09/23/09
4
ICS9FG1201H
Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD
ICS9FG1201 Programmable Gear Ratios
FS_A_410
SMBus
Byte 0
Bit 3
Bit 2
Bit 1
Bit 0
Input Output Gear Ratio
(m)
(n)
(n/m)
Input (CPU FSB) and Output
Frequencies (MHz)
200.0
3
5
12
2
5
8
3
4
6
1
5
4
3
2
3
1
1
2
5
1
3
5
2
3
5
1
6
5
4
3
5
2
0.333
0.400
0.417
0.500
0.600
0.625
0.667
0.750
0.833
1.000
1.200
1.250
1.333
1.500
1.667
2.000
266.7
320.0
333.3
400.0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
66.7
88.9
106.7
111.1 133.3
80.0 106.7
128.0
133.3 160.0
83.3 111.1
133.3
138.9 166.7
100.0 133.3
160.0
166.7 200.0
120.0 160.0
192.0
200.0 240.0
125.0 166.7
200.0
208.3 250.0
133.3 177.8
213.3
222.2 266.7
150.0 200.0
240.0
250.0 300.0
166.7 222.2
266.7
277.8 333.3
200.0 266.7
320.0
333.3 400.0
240.0 320.0
384.0
400.0
NA
250.0 333.3
400.0
NA
NA
266.7 355.6
NA
NA
NA
300.0 400.0
NA
NA
NA
333.3
NA
NA
NA
NA
400.0
NA
NA
NA
NA
CLK IN (CPU FSB) Frequency (MHz)
100 133.33
160
166.67
1 0 0 0 0
3
1
0.333
1 0 0 0 1
5
2
0.400
NA
53.3
64.0
66.7
1 0 0 1 0
12
5
0.417
NA
55.6
66.7
69.4
1 0 0 1 1
2
1
0.500
50.0
66.7
80.0
83.3
1 0 1 0 0
5
3
0.600
60.0
80.0
96.0
100.0
1 0 1 0 1
8
5
0.625
62.5
83.3
100.0
104.2
1 0 1 1 0
3
2
0.667
66.7
88.9
106.7
111.1
1 0 1 1 1
5
4
0.800
80.0 106.7
128.0
133.3
1 1 0 0 0
6
5
0.833
NA
111.1
133.3
138.9
1 1 0 0 1
1
1
1.000
100.0 133.3
160.0
166.7
1 1 0 1 0
5
6
1.200
120.0 160.0
192.0
200.0
1 1 0 1 1
4
5
1.250
125.0 166.7
200.0
208.3
1 1 1 0 0
3
4
1.333
133.3 177.8
213.3
222.2
1 1 1 0 1
2
3
1.500
150.0 200.0
1 1 1 1 0
3
5
1.667
166.7 222.2
266.7
277.8
1 1 1 1 1
1
2
2.000
200.0 266.7
320.0
333.3
Note: Lines in
BOLD
are Power-up defaults for FS_A_410 = 0 and 1 respectively.
Shaded areas are shown for reference only and are not necessarily valid operating points
IDT
TM
/ICS
TM
Frequency Gearing Clock for CPU, PCIe Gen1, Gen2, & FBD
1371F — 09/23/09
5
