DATASHEET
Four Output Differential Frequency Generator
for PCIe Gen3 and QPI
General Description:
The 9FG430 is a Frequency Timing Generator that provides 4
HCSL differential output pairs. These outputs support PCI-Express
Gen3, and QPI applications. The part supports Spread Spectrum
and synthesizes several additional output frequencies from either
a 14.31818 MHz crystal, a 25 MHz crystal or reference input clock.
The 9FG430 also outputs a copy of the reference clock. Complete
control of the device is available via strapping pins or via the
SMBus inteface.
9FG430
Features/Benefits:
•
•
•
•
•
Pin-to-Pin with 9FG104D/Easy upgrade to PCIe Gen3
Generates common frequencies from 14.318 MHz or 25
MHz; single part supports mulitple applications
Provides copy of reference output; eleminates need for
additional crystal or oscillator
Unused outputs may be disabled in Hi-Z; save system
power
Device may be configured by SMBus and/or strap pins;
can be used in systems without SMBus
Recommended Application:
4 Output Differential Frequency Generator for PCIe Gen3 and QPI
Key Specifications:
•
•
•
•
•
Cycle-to-cycle jitter: < 50ps with 25MHz input
Output-to-output skew: <50ps
Phase jitter: PCIe Gen3 < 1ps rms
Phase jitter: QPI 9.6GB/s < 0.2ps rms
10 ppm synthesis error with 25MHz input and Spread Off
Output Features:
•
•
4 - 0.7V current mode differential HCSL output pairs
1 - 3.3V LVTTL REF output
Functional Block Diagram
XIN/CLKIN
X2
OSC
REFOUT
PROGRAMMABLE
SPREAD PLL
STOP
LOGIC
4
DIF(3:0)
SPREAD
SEL14M_25M#
DIF_STOP#
FS(2:0)
SDATA
SCLK
CONTROL
LOGIC
IREF
IDT
®
Four Output Differential Frequency Generator for PCIe Gen3 and QPI
1681D—04/04/17
1
9FG430
Four Output Differential Frequency Generator for PCIe Gen3 and QPI
Pin Configuration
XIN/CLKIN
X2
VDD
GND
REFOUT
vFS2
DIF_3
DIF_3#
VDD
GND
DIF_2
DIF_2#
SDATA
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDDA
GNDA
IREF
vFS0
vFS1
DIF_0
DIF_0#
VDD
GND
DIF_1
DIF_1#
^SEL14M_25M#
vSPREAD
DIF_STOP#
^ indicates internal 120K pull up
v indicates internal 120K pull down
Power Groups
Pin Number
VDD
GND
3
4
9,21
10,20
28
27
Frequency Select Table
SEL14M_25M#
FS2 FS1 FS0 OUTPUT (MHz)
(FS3)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
100.00
125.00
133.33
166.67
200.00
266.67
333.33
400.00
100.00
125.00
133.33
166.67
200.00
266.67
333.33
400.00
1681D—04/04/17
Description
REFOUT, Digital Inputs
DIF Outputs
IREF, Analog VDD, GND for PLL Core
IDT
®
Four Output Differential Frequency Generator for PCIe Gen3 and QPI
9FG430
2
9FG430
Four Output Differential Frequency Generator for PCIe Gen3 and QPI
Pin Description
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Note:
PIN NAME
XIN/CLKIN
X2
VDD
GND
REFOUT
vFS2
DIF_3
DIF_3#
VDD
GND
DIF_2
DIF_2#
SDATA
SCLK
DIF_STOP#
vSPREAD
^SEL14M_25M#
DIF_1#
DIF_1
GND
VDD
DIF_0#
DIF_0
vFS1
vFS0
IREF
GNDA
VDDA
PIN TYPE
IN
OUT
PWR
PWR
OUT
IN
OUT
OUT
PWR
PWR
OUT
OUT
I/O
IN
IN
IN
IN
OUT
OUT
PWR
PWR
OUT
OUT
IN
IN
OUT
PWR
PWR
DESCRIPTION
Crystal input or Reference Clock input
Crystal output, Nominally 14.318MHz
Power supply, nominal 3.3V
Ground pin.
Reference Clock output
Frequency select pin. This pin has an internal 120k pull down resistor
0.7V differential true clock output
0.7V differential Complementary clock output
Power supply, nominal 3.3V
Ground pin.
0.7V differential true clock output
0.7V differential Complementary clock output
Data pin for SMBus circuitry, 5V tolerant.
Clock pin of SMBus circuitry, 5V tolerant.
Active low input to stop differential output clocks.
Asynchronous, active high input to enable spread spectrum functionality. This pin
has a 120Kohm pull down resistor.
Select 14.31818 MHz or 25 Mhz input frequency. This pin has an internal 120kohm
pull up resistor.
1 = 14.31818 MHz, 0 = 25 MHz
0.7V differential Complementary clock output
0.7V differential true clock output
Ground pin.
Power supply, nominal 3.3V
0.7V differential Complementary clock output
0.7V differential true clock output
Frequency select pin.
Frequency select pin.
This pin establishes the reference for the differential current-mode output pairs. It
requires a fixed precision resistor to ground. 475ohm is the standard value for
100ohm differential impedance. Other impedances require different values. See
data sheet.
Ground pin for the PLL core.
3.3V power for the PLL core.
^ indicates internal 120K pull up
v indicates internal 120K pull down
IDT
®
Four Output Differential Frequency Generator for PCIe Gen3 and QPI
1681D—04/04/17
3
9FG430
Four Output Differential Frequency Generator for PCIe Gen3 and QPI
Electrical Characteristics - Absolute Maximum Ratings
PARAMETER
3.3V Core Supply Voltage
3.3V Logic Supply Voltage
Input Low Voltage
Input High Voltage
Input High Voltage
Storage Temperature
Junction Temperature
Input ESD protection
1
2
SYMBOL
VDDA
VDD
V
IL
V
IH
V
IHSMB
Ts
Tj
ESD prot
CONDITIONS
MIN
TYP
MAX
4.6
4.6
V
DD
+0.5V
5.5V
UNITS NOTES
V
V
V
V
V
°
GND-0.5
Except for SMBus interface
SMBus clock and data pins
-65
Human Body Model
2000
150
125
C
°C
V
1,2
1,2
1
1
1
1
1
1
Guaranteed by design and characterization, not 100% tested in production.
Operation under these conditions is neither implied nor guaranteed.
Electrical Characteristics - Input/Supply/Common Parameters
TA = TCOM or TIND; Supply Voltage VDD = 3.3 V +/-5%; See Test Loads s for loading conditions.
PARAMETER
Ambient Operating
Temperature
Input High Voltage
Input Low Voltage
SYMBOL
T
COM
T
IND
V
IH
V
IL
I
IN
Input Current
I
INP
CONDITIONS
Commmercial range
Industrial range
Single-ended inputs, except SMBus, low
threshold and tri-level inputs
Single-ended inputs, except SMBus, low
threshold and tri-level inputs
Single-ended inputs, V
IN
= GND, V
IN
= VDD
Single-ended inputs
V
IN
= 0 V; Inputs with internal pull-up resistors
V
IN
= VDD; Inputs with internal pull-down resistors
SEL14M_25M# = 0
SEL14M_25M# = 1
Logic Inputs, except DIF_IN
Crystal inputs
Output pin capacitance
From V
DD
Power-Up and after input clock
stabilization or de-assertion of PD# to 1st clock
Allowable Frequency
(Triangular Modulation)
DIF start after OE# assertion
DIF stop after OE# deassertion
DIF output enable after
PD# de-assertion
Fall time of control inputs
Rise time of control inputs
30
1.5
MIN
0
-40
2
GND - 0.3
-5
-200
25
14.31818
7
5
6
6
1.8
TYP
MAX
70
85
V
DD
+ 0.3
0.8
5
200
UNITS NOTES
°C
°C
V
V
uA
uA
MHz
MHz
nH
pF
pF
pF
ms
1
1
1
1
1
1
1
1
1
1
1,4
1
1,2
Input Frequency
Pin Inductance
Capacitance
F
in
L
pin
C
IN
C
INXTAL
C
OUT
Clk Stabilization
Input SS Modulation
Frequency
OE# Latency
Tdrive_PD#
Tfall
Trise
SMBus Input Low Voltage
SMBus Input High Voltage
SMBus Output Low Voltage
SMBus Sink Current
Nominal Bus Voltage
SCLK/SDATA Rise Time
SCLK/SDATA Fall Time
SMBus Operating
Frequency
1
2
T
STAB
f
MODIN
33
kHz
1
t
LATOE#
t
DRVPD
t
F
t
R
V
ILSMB
V
IHSMB
V
OLSMB
I
PULLUP
V
DDSMB
t
RSMB
t
FSMB
f
MAXSMB
1
3
300
5
5
0.8
cycles
us
ns
ns
V
V
V
mA
V
ns
ns
kHz
1,3
1,3
1,2
1,2
1
1
1
1
1
1
1
1,5
2.1
@ I
PULLUP
@ V
OL
3V to 5V +/- 10%
(Max VIL - 0.15) to (Min VIH + 0.15)
(Min VIH + 0.15) to (Max VIL - 0.15)
Maximum SMBus operating frequency
4
2.7
V
DDSMB
0.4
5.5
1000
300
100
Guaranteed by design and characterization, not 100% tested in production.
Control input must be monotonic from 20% to 80% of input swing.
3
Time from deassertion until outputs are >200 mV
4
DIF_IN input
The differential input clock must be running for the SMBus to be active
IDT
®
Four Output Differential Frequency Generator for PCIe Gen3 and QPI
5
1681D—04/04/17
4
9FG430
Four Output Differential Frequency Generator for PCIe Gen3 and QPI
Electrical Characteristics - DIF 0.7V Current Mode Differential Outputs
TA = TCOM or TIND; Supply Voltage VDD = 3.3 V +/-5%; See Test Loads s for loading conditions.
PARAMETER
Slew rate
Slew rate matching
Voltage High
Voltage Low
Max Voltage
Min Voltage
Vswing
Crossing Voltage (abs)
Crossing Voltage (var)
1
SYMBOL
Trf
∆
Trf
VHigh
VLow
Vmax
Vmin
Vswing
Vcross_abs
∆
-Vcross
CONDITIONS
Scope averaging on
Slew rate matching, Scope averaging on
Statistical measurement on single-ended signal
using oscilloscope math function. (Scope
averaging on)
Measurement on single ended signal using
absolute value. (Scope averaging off)
Scope averaging off
Scope averaging off
Scope averaging off
MIN
1
660
-150
-300
300
250
TYP
MAX UNITS NOTES
V/ns
1, 2, 3
4
%
20
1, 2, 4
850
mV
150
1150
mV
mV
mV
mV
1
1
1
1, 2
1, 5
1, 6
1
550
140
Guaranteed by design and characterization, not 100% tested in production. IREF = VDD/(3xR
R
). For R
R
= 475
Ω
(1%), I
REF
= 2.32mA.
I
OH
= 6 x I
REF
and V
OH
= 0.7V @ Z
O
=50
Ω
(100
Ω
differential impedance).
2
3
Measured from differential waveform
Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around
differential 0V.
Matching applies to rising edge rate of Clock / falling edge rate of Clock#. It is measured in a +/-75mV window centered on the
average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the
oscilloscope uses for the edge rate calculations.
Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising
edge (i.e. Clock rising and Clock# falling).
The total variation of all Vcross measurements in any particular system. Note that this is a subset of V_cross_min/max (V_cross
absolute) allowed. The intent is to limit Vcross induced modulation by setting V_cross_delta to be smaller than V_cross absolute.
6
5
4
Electrical Characteristics - Current Consumption
TA = TCOM or TIND; Supply Voltage VDD = 3.3 V +/-5%, See Test Loads for loading
PARAMETER
SYMBOL
I
DD3.3
Operating Supply Current
I
DDA3.3OP
I
DD3.3
I
DDA3.3OP
I
DD3.3PD
I
DDA3.3PD
I
DD3.3PDZ
I
DDA3.3PDZ
CONDITIONS
VDD, All outputs active @100MHz
VDDA, All outputs active @100MHz
VDD, All outputs active @400MHz
VDDA, All outputs active @400MHz
VDD, All differential pairs driven
VDDA, All differential pairs driven
VDD, All differential pairs tri-stated
VDDA, All differential pairs tri-stated
MIN
TYP
80
25
100
25
75
25
25
25
MAX
95
30
120
30
90
30
30
30
UNITS NOTES
mA
mA
mA
mA
mA
mA
mA
mA
1
1
1
1
1
1
1
1
Powerdown Current
1
2
Guaranteed by design and characterization, not 100% tested in production.
I
REF
= V
DD
/(3xR
R
). For R
R
= 475
Ω
(1%), I
REF
= 2.32mA. I
OH
= 6 x I
REF
and V
OH
= 0.7V @ Z
O
=50
Ω
.
Electrical Characteristics - Output Duty Cycle, Jitter, and Skew Characterisitics
TA = TCOM or TIND; Supply Voltage VDD = 3.3 V +/-5%, See Test Loads for loading
PARAMETER
Duty Cycle
Skew, Output to Output
Jitter, Cycle to cycle
Jitter, Cycle to cycle
1
2
SYMBOL
t
DC
t
sk3
t
jcyc-cyc
t
jcyc-cyc
CONDITIONS
Measured differentially, PLL Mode
V
T
= 50%
25M input
14.318M input
MIN
45
TYP
MAX
55
50
50
60
UNITS NOTES
%
ps
ps
ps
1
1
1,3
1,3
Guaranteed by design and characterization, not 100% tested in production.
I
REF
= V
DD
/(3xR
R
). For R
R
= 475
Ω
(1%), I
REF
= 2.32mA. I
OH
= 6 x I
REF
and V
OH
= 0.7V @ Z
O
=50
Ω
.
3
Measured from differential waveform
4
Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode.
IDT
®
Four Output Differential Frequency Generator for PCIe Gen3 and QPI
1681D—04/04/17
5
