4-output 3.3V PCIe Gen 1-2-3 Clock Generator
9FGL04
DATASHEET
Description
The 9FGL0441/51/P1 are members of IDT's 3.3V Low-Power
(LP) PCIe family. The devices have 4 output enables for
clock management and support 2 different spread spectrum
levels in addition to spread off. The 9FGL0441/51/P1
supports both Common Clock (CC) with or without spread
spectrum and Separate Reference no-Spread (SRnS) PCIe
clocking architectures. The 9FGL04P1 can be programmed
with a user-defined power up default SMBus configuration.
Features/Benefits
•
Direct connection to 100 (xx41) or 85 (xx51)
•
•
transmission lines; saves 16 resistors compared to
standard PCIe devices
142mW typical power consumption; eliminates thermal
concerns
SMBus-selectable features allows optimization to customer
requirements:
•
control input polarity
•
control input pull up/downs
•
slew rate for each output
•
33, 85 or 100Ω output impedance for each output
•
spread spectrum amount
41 and 51 devices contain default configuration; SMBus
interface not required for device operation
P1 device allows factory programming of customer-defined
SMBus power up default; allows exact optimization to
customer requirements
OE# pins; support DIF power management
8MHz – 40MHz input frequency (25MHz default); flexibility
Pin/SMBus selectable 0%, -0.25% or -0.5% spread on DIF
outputs %; minimize EMI and phase jitter for each
application
DIF outputs blocked until PLL is locked; clean system
start-up
Two selectable SMBus addresses; multiple devices can
easily share an SMBus segment
Space saving 32-pin 5x5mm VFQFPN; minimal board
space
Recommended Application
3.3V PCIe Gen1-2-3 Clock Generator
Output Features
•
4 – 100 MHz Low-Power HCSL (LP-HCSL) DIF pairs
•
9FGL0441 default Z
OUT
= 100
•
9FGL0451 default Z
OUT
= 85
•
9FGL04P1 factory programmable defaults
•
1 - 3.3V LVCMOS REF output w/Wake-On-LAN (WOL)
support
•
•
•
•
•
•
•
•
Key Specifications
•
DIF cycle-to-cycle jitter <50ps
•
DIF output-to-output skew <50ps
•
DIF phase jitter is PCIe Gen1-2-3 compliant with SSC on or
•
•
•
off
DIF 12k-20M phase jitter is <3ps rms when SSC is off
REF phase jitter is <300fs rms (SSC off) and < 1ps RMS
(SSC on)
±100ppm frequency accuracy on all clocks
Block Diagram
XIN/CLKIN_25
X2
vOE(3:0)#
OSC
REF3.3
DIF3
SS Capable PLL
DIF2
vSADR
vSS_EN_tri
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
DIF1
CONTROL
LOGIC
DIF0
Note:
Resistors default to internal on 41/51 devices. P1 devices have programmable default impedances on an output-by-output basis.
9FGL04 REVISION B 08/06/15
1
©2015 Integrated Device Technology, Inc.
9FGL04 DATASHEET
Pin Configuration
^CKPWRGD_PD#
vSS_EN_tri
32 31 30 29 28 27 26 25
GNDXTAL 1
XIN/CLKIN_25 2
X2 3
VDDXTAL3.3 4
VDDREF3.3 5
vSADR/REF3.3 6
GNDREF
7
GNDDIG
8
SCLK_3.3
VDDDIG3.3
24 vOE2#
23 DIF2#
VDDO3.3
22 DIF2
21 VDDA3.3
20 GNDA
19 DIF1#
18 DIF1
17 vOE1#
VDDO3.3
vOE3#
DIF3#
DIF0
GND
9FGL04xx
ePAD is
GND
9 10 11 12 13 14 15 16
vOE0#
SDATA_3.3
DIF0#
GND
32-pin VFQFPN, 5x5 mm, 0.5mm pitch
^ prefix indicates internal 120KOhm pull up resistor
v prefix indicates internal 120KOhm pull down resistor
SMBus Address Selection Table
State of SADR on first application
of CKPWRGD_PD#
SADR
0
1
Address
1101000
1101010
+
Read/Write Bit
x
x
Power Management Table
DIFx/DIFx#
OEx#
SMBus
REF
Pin
True O/P
Comp. O/P
OE bit
0
X
X
Low
1
Hi-Z
2
Low
1
1
1
0
Running
Running
Running
1
1
Running
1
1
1
Disabled
Disabled
1
1
1
0
X
Disabled
Disabled
Disabled
4
1. The output state is set by B11[1:0] (Low/Low default)
2. REF is Hi-Z until the 1st assertion of CKPWRGD_PD# high. After this, when
CKPWRG_PD# is low, REF is disabled unless Byte3[5]=1, in which case REF is
running..
3. Input polarities defined at default values for 9FGLxx41/xx51.
4. See SMBus description for Byte 3, bit 4
CKPWRGD_PD#
Power Connections
Pin Number
VDD
4
5
9
16, 25
21
GND
1
7
8, 30
15, 26, 33
20
Description
XTAL Analog
REF Output
Digital Power
DIF outputs
PLL Analog
4-OUTPUT 3.3V PCIE GEN 1-2-3 CLOCK GENERATOR
2
GND
DIF3
REVISION B 08/06/15
9FGL04 DATASHEET
Pin Descriptions
Pin# Pin Name
1
GNDXTAL
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
XIN/CLKIN_25
X2
VDDXTAL3.3
VDDREF3.3
vSADR/REF3.3
GNDREF
GNDDIG
VDDDIG3.3
SCLK_3.3
SDATA_3.3
vOE0#
DIF0
DIF0#
GND
VDDO3.3
vOE1#
DIF1
DIF1#
GNDA
VDDA3.3
DIF2
DIF2#
vOE2#
VDDO3.3
GND
DIF3
DIF3#
vOE3#
GND
^CKPWRGD_PD#
vSS_EN_tri
ePAD
Type
GND
IN
OUT
PWR
PWR
LATCHED
I/O
GND
GND
PWR
IN
I/O
Pin Description
GND for XTAL
Crystal input or Reference Clock input. Nominally 25MHz.
Crystal output.
Power supply for XTAL, nominal 3.3V
VDD for REF output. nominal 3.3V.
Latch to select SMBus Address/3.3V LVCMOS copy of X1/REFIN pin
Ground pin for the REF outputs.
Ground pin for digital circuitry
3.3V digital power (dirty power)
Clock pin of SMBus circuitry, 3.3V tolerant.
Data pin for SMBus circuitry, 3.3V tolerant.
Active low input for enabling DIF pair 0. This pin has an internal pull-down.
IN
1 =disable outputs, 0 = enable outputs
OUT
Differential true clock output
OUT
Differential Complementary clock output
GND
Ground pin.
PWR
Power supply for outputs,nominal 3.3V.
Active low input for enabling DIF pair 1. This pin has an internal pull-down.
IN
1 =disable outputs, 0 = enable outputs
OUT
Differential true clock output
OUT
Differential Complementary clock output
GND
Ground pin for the PLL core.
PWR
3.3V power for the PLL core.
OUT
Differential true clock output
OUT
Differential Complementary clock output
Active low input for enabling DIF pair 2. This pin has an internal pull-down.
IN
1 =disable outputs, 0 = enable outputs
PWR
Power supply for outputs,nominal 3.3V.
GND
Ground pin.
OUT
Differential true clock output
OUT
Differential Complementary clock output
Active low input for enabling DIF pair 3. This pin has an internal pull-down.
IN
1 =disable outputs, 0 = enable outputs
GND
Ground pin.
Input notifies device to sample latched inputs and start up on first high assertion.
Low enters Power Down Mode, subsequent high assertions exit Power Down
IN
Mode. This pin has internal pull-up resistor.
Latched select input to select spread spectrum amount at initial power up :
LATCHED IN
1 = -0.5% spread, M = -0.25%, 0 = Spread Off
GND
Connect to ground
REVISION B 08/06/15
3
4-OUTPUT 3.3V PCIE GEN 1-2-3 CLOCK GENERATOR
9FGL04 DATASHEET
Test Loads
Low-Power Differential Output Test Load
Terminations
Device
9FGL0441
9FGL0451
9FGL04P1
9FGL0441
9FGL0451
9FGL04P1
Zo (Ω)
100
100
100
85
85
85
Rs (Ω)
None needed
7.5
Prog.
N/A
None needed
Prog.
5 inches
Rs
Zo=100ohm
2pF
2pF
Rs
Note: The device can drive transmission line lengths greater
than those specified by the PCIe SIG
REF Output Test Load
Zo = 50 ohms
33
5pF
REF Output
Alternate Terminations
The 9FGL family can easily drive LVPECL, LVDS, and CML logic. See
“AN-891 Driving LVPECL, LVDS, and CML Logic with
IDT's "Universal" Low-Power HCSL Outputs”
for details.
4-OUTPUT 3.3V PCIE GEN 1-2-3 CLOCK GENERATOR
4
REVISION B 08/06/15
9FGL04 DATASHEET
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the 9FGL04. These ratings, which are standard values
for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions
above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating
conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended
operating temperature range.
PARAMETER
3.3V Supply Voltage
Input Voltage
Input High Voltage, SMBus
Storage Temperature
Junction Temperature
Input ESD protection
1
2
SYMBOL
VDDxx
V
IN
V
IHSMB
Ts
Tj
ESD prot
CONDITIONS
Applies to VDD, VDDA and VDDIO, if present.
MIN
-0.5
-0.5
TYP
SMBus clock and data pins
-65
Human Body Model
2000
MAX
3.9
V
DD
+0.5
3.9
150
125
UNITS NOTES
V
V
V
°C
°C
V
1,2
1, 3
1
1
1
1
Guaranteed by design and characterization, not 100% tested in production.
Operation under these conditions is neither implied nor guaranteed.
3
Not to exceed 4.5V.
Electrical Characteristics–SMBus Parameters
TA = T
AMB;
Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SMBus Input Low Voltage
SMBus Input High Voltage
SMBus Output Low Voltage
SMBus Sink Current
Nominal Bus Voltage
SCLK/SDATA Rise Time
SCLK/SDATA Fall Time
SMBus Operating
Frequency
1
SYMBOL
V
ILSMB
V
IHSMB
V
OLSMB
I
PULLUP
V
DDSMB
t
RSMB
t
FSMB
f
MAXSMB
CONDITIONS
V
DDSMB
= 3.3V
V
DDSMB
= 3.3V
@ I
PULLUP
@ V
OL
(Max VIL - 0.15) to (Min VIH + 0.15)
(Min VIH + 0.15) to (Max VIL - 0.15)
Maximum SMBus operating frequency
MIN
TYP
MAX
0.8
3.6
0.4
3.6
1000
300
400
UNITS NOTES
V
V
V
mA
V
ns
ns
kHz
2.1
4
2.7
1
1
Guaranteed by design and characterization, not 100% tested in production.
REVISION B 08/06/15
5
4-OUTPUT 3.3V PCIE GEN 1-2-3 CLOCK GENERATOR
