DATASHEET
6-OUTPUT LOW-POWER DIFFERENTIAL SYNTHESIZER FOR PCIE GEN1/2/3
9FGL639
Description
The 9FGL639 is a 6-output low-power clock sythesizer for
PCIe Gen1/2/3. It runs from a 25MHz XTAL, provides
spread spectrum capability, and has an SMBus for software
control of the device.
Features/Benefits
•
32-pin QFN; Space-savings
•
LP-HCSL outputs/Low power consumption, reduced
•
•
•
•
•
•
•
•
component count
PCIe Gen1/2/3 /Supports latest systems
Spread Spectrum Capability; reduced EMI when needed
D2/D3 SMBus Write/Read SMBus address
Recommended Application
6 - Output Low-Power Differential Synthesizer for PCIe
Gen1/2/3
Key Specifications
Cycle-to-cycle jitter <50ps
Output-to-output skew <100 ps
Current consumption < 50mA
PCIe Gen2 phase jitter <3.0ps RMS
PCIe Gen3 phase jitter <1.0ps RMS
Output Features
•
6 - Differential low power push pull HCSL-compatible
(LP-HCSL) output pairs
Block Diagram
XIN/CLKIN_25
X2_25
OSC
PROGRAMMABLE
SPREAD PLL
STOP
LOGIC
6
DIF(5:0)
CONTROL
LOGIC
SDATA
SCLK
IDT®
6-OUTPUT LOW-POWER DIFFERENTIAL SYNTHESIZER FOR PCIE GEN1/2/3
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9FGL639
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9FGL639
6-OUTPUT LOW-POWER DIFFERENTIAL SYNTHESIZER FOR PCIE GEN1/2/3
Pin Configuration
XIN/CLKIN_25
DIF_3#
32 31 30 29 28 27 26 25
NC
1
VDD
2
NC
3
GND
4
GND
5
DIF_0
6
DIF_0#
7
VDD
8
9 10 11 12 13 14 15 16
DIF_2
DIF_2#
DIF_1#
DIF_1
DIF_3
2
X2_25
24 SMBDAT
23 SMBCLK
22 GND
21
DIF_5
20
DIF_5#
19 VDD
18
DIF_4
17
DIF_4#
GND
9FGL639
GND
Power Management
OE# (SMBUS) Differential Outputs
1
DIF/DIF# = running
0
DIF/DIF# = Low/Low
IDT®
6-OUTPUT LOW-POWER DIFFERENTIAL SYNTHESIZER FOR PCIE GEN1/2/3
VDD
GND
VDD
VDD
NC
NC
9FGL639
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9FGL639
6-OUTPUT LOW-POWER DIFFERENTIAL SYNTHESIZER FOR PCIE GEN1/2/3
Pin Descriptions
Pin# Pin Name
1
NC
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
VDD
NC
GND
GND
DIF_0
DIF_0#
VDD
DIF_1
DIF_1#
DIF_2
DIF_2#
GND
VDD
DIF_3#
DIF_3
DIF_4#
DIF_4
VDD
DIF_5#
DIF_5
GND
SMBCLK
SMBDAT
X2_25
XIN/CLKIN_25
GND
NC
VDD
NC
GND
VDD
Type Pin Description
N/A No Connection.
PWR
N/A
PWR
PWR
OUT
OUT
PWR
OUT
OUT
OUT
OUT
PWR
PWR
OUT
OUT
OUT
OUT
PWR
OUT
OUT
PWR
IN
I/O
OUT
IN
PWR
N/A
PWR
N/A
PWR
PWR
Power supply, nominal 3.3V
No Connection.
Ground pin.
Ground pin.
0.7V differential true clock output
0.7V differential Complementary clock output
Power supply, nominal 3.3V
0.7V differential true clock output
0.7V differential Complementary clock output
0.7V differential true clock output
0.7V differential Complementary clock output
Ground pin.
Power supply, nominal 3.3V
0.7V differential Complementary clock output
0.7V differential true clock output
0.7V differential Complementary clock output
0.7V differential true clock output
Power supply, nominal 3.3V
0.7V differential Complementary clock output
0.7V differential true clock output
Ground pin.
Clock pin of SMBUS circuitry, 5V tolerant
Data pin of SMBUS circuitry, 5V tolerant
Crystal output, Nominally 25.00MHz.
Crystal input or Reference Clock input. Nominally 25MHz.
Ground pin.
No Connection.
Power supply, nominal 3.3V
No Connection.
Ground pin.
Power supply, nominal 3.3V
IDT®
6-OUTPUT LOW-POWER DIFFERENTIAL SYNTHESIZER FOR PCIE GEN1/2/3
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9FGL639
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6-OUTPUT LOW-POWER DIFFERENTIAL SYNTHESIZER FOR PCIE GEN1/2/3
General SMBus Serial Interface Information for 9FGL639
How to Write
How to Read
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•
•
•
•
•
•
•
•
•
Controller (host) sends a start bit
Controller (host) sends the write address
IDT clock will
acknowledge
Controller (host) sends the beginning byte location = N
IDT clock will
acknowledge
Controller (host) sends the byte count = X
IDT clock will
acknowledge
Controller (host) starts sending Byte
N through Byte
N+X-1
IDT clock will
acknowledge
each byte
one at a time
Controller (host) sends a Stop bit
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Index Block Write Operation
Controller (Host)
T
WR
starT bit
Slave Address
WRite
ACK
Beginning Byte = N
ACK
Data Byte Count = X
ACK
Beginning Byte N
ACK
O
O
O
Byte N + X - 1
ACK
P
stoP bit
X Byte
O
O
O
IDT (Slave/Receiver)
Controller (host) will send a start bit
Controller (host) sends the write address
IDT clock will
acknowledge
Controller (host) sends the beginning byte location = N
IDT clock will
acknowledge
Controller (host) will send a separate start bit
Controller (host) sends the read address
IDT clock will
acknowledge
IDT clock will send the data byte count = X
IDT clock sends Byte
N+X-1
IDT clock sends
Byte 0 through Byte X (if X
(H)
was
written to Byte 8)
Controller (host) will need to acknowledge each byte
Controller (host) will send a not acknowledge bit
Controller (host) will send a stop bit
Index Block Read Operation
Controller (Host)
T
WR
starT bit
Slave Address
WRite
ACK
Beginning Byte = N
ACK
RT
RD
Repeat starT
Slave Address
ReaD
ACK
Data Byte Count=X
ACK
Beginning Byte N
ACK
X Byte
O
O
O
Byte N + X - 1
N
P
Not acknowledge
stoP bit
O
O
O
IDT (Slave/Receiver)
Read Address
D2
(H)
Write Address
D3
(H)
IDT®
6-OUTPUT LOW-POWER DIFFERENTIAL SYNTHESIZER FOR PCIE GEN1/2/3
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9FGL639
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6-OUTPUT LOW-POWER DIFFERENTIAL SYNTHESIZER FOR PCIE GEN1/2/3
SMBus Table: Device Control Register, READ/WRITE ADDRESS (D2/D3)
Byte 0
Pin #
Name
Control Function
Type
-
Reserved
Bit 7
-
Reserved
Bit 6
Spread Enable
RW
Bit 5
-
Reserved
Bit 4
-
Reserved
Bit 3
-
Reserved
Bit 2
-
P
Bit 1
-
Reserved
Bit 0
SMBus Table: Output Enable Register
Byte 1
Pin #
Name
-
Bit 7
-
DIF_0 EN
Bit 6
-
Bit 5
-
Bit 4
-
DIF_1 EN
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
SMBus Table: Reserved Register
Byte 2
Pin #
Name
-
Bit 7
-
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
SMBus Table: Output Enable Register
Byte 3
Pin #
Name
-
DIF_5 EN
Bit 7
-
DIF_4 EN
Bit 6
-
Bit 5
-
Bit 4
-
Bit 3
-
Bit 2
-
Bit 1
-
Bit 0
0
1
Off
-0.50%
Default
0
0
1
0
0
0
0
0
Control Function
Type
Reserved
Output Enable
RW
Reserved
Reserved
Output Enable
RW
Reserved
Reserved
Reserved
0
Disable
1
Enable
Disable
Enable
Default
0
1
0
0
1
0
0
0
Control Function
Type
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0
1
Default
0
0
0
0
0
0
0
0
Control Function
Type
Output Enable
RW
Output Enable
RW
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
0
Disable
Disable
1
Enable
Enable
Default
1
1
0
0
0
0
0
0
IDT®
6-OUTPUT LOW-POWER DIFFERENTIAL SYNTHESIZER FOR PCIE GEN1/2/3
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9FGL639
REV A 061312
