DATASHEET
Frequency Timing Generator for Peripherals
Vtt_PWRGD/WOL_STOP#
9FGP205
Recommended Application:
Peripheral Clock for Intel Servers with Wake-On-Lan support
Output Features:
•
1 - 0.7V current-mode differential CPU output
•
6 - 50MHz RMII outputs
•
2 - 125MHz RGMII outputs
•
1 - 0.7V current-mode differential DOT 96MHz output
•
1 - 33.33MHz output
•
1 - 32.768KHz output
•
2 - 25MHz REF outputs
Key Specifications:
•
Exact synthesis on CPU, RGMII, RMII & 33.33MHz
clocks
•
+/- 100ppm frequency accuracy on other clocks
Features/Benefits:
•
Selectable SMBus Address - D0/D1 or C0/C1
•
Spread Spectrum capability on CPU and DOT 96MHz
clocks
•
SMBus Control:
- M/N and spread programming on CPU and DOT
96MHz clocks via SMBus
- Differential outputs can be disabled via pins or SMBus
Pin Configuration
GNDRGMII
VDDRGMII
SMBDAT
40 39 38 37 36 35 34 33 32 31
GND
VDD96
DOT96SST
DOT96SSC
OE_96
OE_CPU
CPUCLKT0
CPUCLKC0
VDDCPU
GNDCPU
1
2
3
4
5
6
7
8
9
10
IREF
VDD32K
32.768KHz
30
29
28
27
26
25
24
23
22
21
X1_25
GNDREF
X2_25
GNDRMII
RMII2
RMII3
GNDRMII
VDDRMII
RMII4
RMII5
VDD33
33.33MHZ/**SMBADR
GND33
9FGP205
11 12 13 14 15 16 17 18 19 20
25MHz_0
25MHZ_1
VDDREF
GND32K
40-MLF
* Internal Pull-Up Resistor
** Internal Pull-Dow n Resistor
Functionality
CPU FS2 CPU FS1 CPU FS0 CPUCLK DOT96SS
MHz
MHz
Byte0 Bit2 Byte0 Bit1 Byte0 Bit0
0
0
0
266.67
96.00
0
0
1
133.33
96.00
0
1
0
200.00
96.00
0
1
1
166.67
96.00
1
0
0
333.33
96.00
1
0
1
100.00
96.00
1
1
0
400.00
96.00
1
1
1
Reserved
96.00
Power up default is highlighted.
33.33
MHz
33.33
33.33
33.33
33.33
33.33
33.33
33.33
33.33
RMII
MHz
50.00
50.00
50.00
50.00
50.00
50.00
50.00
50.00
RGMII
MHz
125.00
125.00
125.00
125.00
125.00
125.00
125.00
125.00
25
MHz
25.00
25.00
25.00
25.00
25.00
25.00
25.00
25.00
32.768
KHz
32.768
32.768
32.768
32.768
32.768
32.768
32.768
32.768
SMBus Address Selection
SMBADR
SMBADR = 0
D0/D1
SMBADR = 1
C0/C1
IDT
®
Frequency Timing Generator for Peripherals
VDDRMII
SMBCLK
RGMII0
RGMII1
RMII0
RMII1
1664—07/16/14
1
9FGP205
Frequency Timing Generator for Peripherals
Pin Description
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
GND
VDD96
DOT96SST
DOT96SSC
OE_96
OE_CPU
CPUCLKT0
CPUCLKC0
VDDCPU
GNDCPU
IREF
VDD32K
32.768KHz
GND32K
VDDREF
25MHz_0
25MHZ_1
GNDREF
X1_25
X2_25
GND33
33.33MHZ/**SMBADR
VDD33
RMII5
RMII4
VDDRMII
GNDRMII
RMII3
RMII2
GNDRMII
VDDRMII
RMII1
RMII0
VDDRGMII
GNDRGMII
RGMII1
RGMII0
SMBCLK
SMBDAT
CKPWRGD_WOL_STOP#
PIN NAME
PIN
TYPE
PWR
PWR
OUT
OUT
IN
IN
OUT
OUT
PWR
PWR
OUT
PWR
OUT
PWR
PWR
OUT
OUT
PWR
IN
OUT
PWR
I/O
PWR
OUT
OUT
PWR
PWR
OUT
OUT
PWR
PWR
OUT
OUT
PWR
PWR
OUT
OUT
IN
I/O
IN
DESCRIPTION
Ground pin.
Power pin for the DOT96 clocks, nominal 3.3V
True clock of differential pair for 96.00MHz spread spectrum capable DOT clock. These are
current mode outputs. External resistors are required for voltage bias.
Complementary clock of differential pair for 96.00MHz spread spectrum capable DOT clock.
These are current mode outputs. External resistors are required for voltage bias.
Active high input for enabling 96Hz outputs.
1 = enable output(s), 0 = tri-state output(s)
Active high input for enabling CPU DIFF pairs.
1 = enable output(s), 0 = tri-state output(s)
True clock of differential pair CPU outputs. These are current mode outputs. External resistors
are required for voltage bias.
Complementary clock of differential pair CPU outputs. These are current mode outputs.
External resistors are required for voltage bias.
Supply for CPU clocks, 3.3V nominal
Ground pin for the CPU outputs
This pin establishes the reference current for the differential current-mode output pairs. This pin
requires a fixed precision resistor tied to ground in order to establish the appropriate current.
475 ohms is the standard value.
Power pin for the 32.768KHz outputs, nominal 3.3V
32.768KHz clock output
Ground pin for the 32.768KHz outputs
Ref, XTAL power supply, nominal 3.3V
25MHz clock output, 3.3V
25MHz clock output, 3.3V
Ground pin for the REF outputs.
Crystal input, Nominally 25.00MHz.
Crystal output, Nominally 25.00MHz.
Ground pin for the 33.33MHz outputs
33.33MHz clock output / SMBus address select bit.
Power pin for the 33.33MHz outputs, nominal 3.3V
3.3V 50MHz RMII clock output
3.3V 50MHz RMII clock output
3.3V power pin for the RMII clocks.
Ground pin for the RMII outputs
3.3V 50MHz RMII clock output
3.3V 50MHz RMII clock output
Ground pin for the RMII outputs
3.3V power pin for the RMII clocks.
3.3V 50MHz RMII clock output
3.3V 50MHz RMII clock output
3.3V power pin for the RGMII clocks and PLL
Ground pin for the RGMII outputs
3.3V 125MHz RGMII clock output
3.3V 125MHz RGMII clock output
Clock pin of SMBUS circuitry, 5V tolerant
Data pin of SMBUS circuitry, 5V tolerant
Notifies clock to sample latched inputs on first low to high transition. After first power up, a low
stops all outputs except those designated to run in power down mode (WOL_STOP# mode)
IDT
®
Frequency Timing Generator for Peripherals
1664—07/16/14
2
9FGP205
Frequency Timing Generator for Peripherals
General Description
The
9FGP205
is a peripheral clock for Intel Servers. It is driven with a 25MHz crystal and generates a variety of clocks,
including 125MHz RGMII. An SMBus interface allows full control of the device.
Block Diagram
25MHz(1:0)
X1_25
X2_25
XTAL
CPU PLL
(SPREAD
CAPABLE)
CPUCLK
DOT PLL
(SPREAD
CAPABLE)
CKPWRGD_
WOL_STOP#
OE_CPU
OE_96
SMBADR
SMBDAT
SMBCLK
DIVIDERS
CONTROL
LOGIC
FIXED
PLL
DIVIDERS
2
6
DOT96SS
33.33MHz
RGMII(1:0)
RMII(5:0)
32.768KHz
Power Supply Pins
Pin Number
Description
VDD
GND
9
10
CPUCLK output and PLL
2
1
DOT96SS output and PLL
34
35
125 MHz RGMII outputs and PLL
26,31
27,30
50 MHz RMII outputs
23
21
33.33MHz output
12
14
32.768KHz output
15
18
XTAL, REF outputs
Note: All VDD should be connected to a common power rail with proper
filtering and decoupling. Pins 2, 9 and 34 should be treated as analog pins for
decoupling purposes.
IDT
®
Frequency Timing Generator for Peripherals
1664—07/16/14
3
9FGP205
Frequency Timing Generator for Peripherals
ICS9FGP202A
ICS9FGP205
Zo
Rs
CL=5pF
SEPP Output Buffer
(Single Ended
Push Pull)
Test Load
L1
Zo
Rs
L2
CL=5pF
Zo
Rs
SEPP Output Buffer
(Single Ended
Push Pull)
CL=5pF
NOTE: L1 must equal L2 +/- 25 mils
Drive Strength for all the single-ended outputs can be controlled by the SMBus Bytes 4 and 5 as shown in the Default Drive Strength Table.
Default Drive Strength Table
Default Drive
RGMII
1 Load
RMII
1 Load
33.33MHz
2 Loads
25Mhz
2 Loads
32.768KHz
2 Loads
Optional Drive
NA
2 Loads
1 Load
1 Load
1 Load
Series Termination Resistor Values EXCEPT RGMII
Series Resistor Series Resistor
Output Drive
(Rs) for driving 1 (Rs) for driving 2
Loads
Load
Strength
1 Load
22 ohms
N/A
2 Loads
33 ohms
8.2 ohms
Note: All values are for Zo = 50
Ω
Series Termination Resistor Values - RGMII
Series Resistor Series Resistor
Output Drive
(Rs) for driving 1 (Rs) for driving 2
Loads
Load
Strength
1 Load
27 ohms
N/A
Note: All values are for Zo = 50
Ω
IDT
®
Frequency Timing Generator for Peripherals
1664—07/16/14
4
9FGP205
Frequency Timing Generator for Peripherals
Truth Table1: CKPWRGD_WOL_STOP#, OE_96 and OE_CPU
CKPWRGD_WOL_STOP#
OE_96
DOT96SSC OE_CPU
0
X
X
X
0
1
0
Disabled
0
1
1
Enabled
1
*Assuming DOT96 Output Enable from SMBus Byte2 Bit0 sets to enable (default)
*Assuming CPUCLK Output Enable from SMBus Byte2 Bit1 sets to enable (default)
CPUCLK
X
Disabled
Enabled
Truth Table 2: CKPWRGD_WOL_STOP# Single-ended outputs
Other
Pin 16, 29,
Pin 22
CKPWRGD_WOL_STOP#
outputs
32, 33
0
Running
Hi-Z
Low
1
Running
Running
Running
*Assuming SMBus at default value.
Table: CPU Spread and Frequency Selection
CPU
SS_EN
Byte 0
Bit 3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
CPU
FS2
Byte 0
Bit 2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
CPU
FS1
Byte 0
Bit 1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
CPU
FS0
Byte 0
Bit 0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CPU
MHz
266.67
133.33
200.00
166.67
333.33
100.00
400.00
200.00
266.67
133.33
200.00
166.67
333.33
100.00
400.00
200.00
Down
Spread %
0%
0%
0%
0%
0%
0%
0%
0%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
0.5%
IDT
®
Frequency Timing Generator for Peripherals
1664—07/16/14
5
