4 O/P 1.5V PCIe Gen1-2-3 Clock Generator
9FGU0431
DATASHEET
Description
The 9FGU0431 is a member of IDT's 1.5V Ultra-Low-Power
PCIe clock family. The device has 4 output enables for clock
management, 2 different spread spectrum levels in addition to
spread off and 2 selectable SMBus addresses.
Features/Benefits
•
LP-HCSL outputs; save 8 resistors compared to standard
•
•
•
•
•
•
•
PCIe device
39mW typical power consumption; reduced thermal
concerns
OE# pins; support DIF power management
Programmable Slew rate for each output; allows tuning for
various line lengths
Programmable output amplitude; allows tuning for various
application environments
DIF outputs blocked until PLL is locked; clean system
start-up
Selectable 0%, -0.25% or -0.5% spread on DIF outputs;
reduces EMI
External 25MHz crystal; supports tight ppm with 0 ppm
synthesis error
Configuration can be accomplished with strapping pins;
SMBus interface not required for device control
Selectable SMBus addresses; multiple devices can easily
share an SMBus segment
3.3V tolerant SMBus interface works with legacy controllers
Space saving 32-pin 5x5 mm VFQFPN; minimal board
space
Recommended Application
1.5V PCIe Gen1-2-3 Clock Generator
Output Features
•
4 - 100MHz Low-Power (LP) HCSL DIF pair
•
1 - 1.5V LVCMOS REF output w/Wake-On-LAN (WOL)
support
Key Specifications
•
•
•
•
DIF cycle-to-cycle jitter <50ps
DIF output-to-output skew <50ps
DIF phase jitter is PCIe Gen1-2-3 compliant
REF phase jitter is < 3.0ps RMS
•
•
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•
Block Diagram
XIN/CLKIN_25
X2
vOE(3:0)#
OSC
REF1.5
DIF3
SS Capable PLL
DIF2
vSADR
vSS_EN_tri
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
DIF1
CONTROL
LOGIC
DIF0
9FGU0431 OCTOBER 18, 2016
1
©2016 Integrated Device Technology, Inc.
9FGU0431 DATASHEET
Pin Configuration
^CKPWRGD_PD#
vSS_EN_tri
32 31 30 29 28 27 26 25
GNDXTAL 1
XIN/CLKIN_25 2
X2 3
VDDXTAL1.5 4
VDDREF1.5 5
vSADR/REF1.5 6
GNDREF
7
GNDDIG
8
9 10 11 12 13 14 15 16
SDATA_3.3
SCLK_3.3
vOE0#
VDDDIG1.5
DIF0#
GND
DIF0
VDDO1.5
24 vOE2#
23 DIF2#
22 DIF2
21 VDDA1.5
20 GNDA
19 DIF1#
18 DIF1
17 vOE1#
9FGU0431
32-pin VFQFPN, 5x5 mm, 0.5mm pitch
^ prefix indicates internal 120KOhm pull up resistor
v prefix indicates internal 120KOhm pull down resistor
SMBus Address Selection Table
State of SADR on first application
of CKPWRGD_PD#
SADR
0
1
Address
1101000
1101010
+
Read/Write Bit
x
x
Power Management Table
SMBus
DIFx
REF
OEx#
True O/P
Comp. O/P
OE bit
0
X
X
Low
Low
Hi-Z
1
1
1
0
Running
Running
Running
1
0
1
Low
Low
Low
1. REF is Hi-Z until the 1st assertion of CKPWRGD_PD# high. After this, when
CKPWRG_PD# is low, REF is Low.
CKPWRGD_PD#
Power Connections
Pin Number
VDD
4
5
9
16, 25
21
GND
1
7
8, 30
15, 26
20
Description
XTAL Analog
REF Output
Digital Power
DIF outputs
PLL Analog
4 O/P 1.5V PCIE GEN1-2-3 CLOCK GENERATOR
2
VDDO1.5
vOE3#
DIF3#
GND
GND
DIF3
OCTOBER 18, 2016
9FGU0431 DATASHEET
Pin Descriptions
Pin# Pin Name
1
GNDXTAL
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
XIN/CLKIN_25
X2
VDDXTAL1.5
VDDREF1.5
vSADR/REF1.5
GNDREF
GNDDIG
VDDDIG1.5
SCLK_3.3
SDATA_3.3
vOE0#
DIF0
DIF0#
GND
VDDO1.5
vOE1#
DIF1
DIF1#
GNDA
VDDA1.5
DIF2
DIF2#
vOE2#
VDDO1.5
GND
DIF3
DIF3#
vOE3#
GND
^CKPWRGD_PD#
vSS_EN_tri
Type
GND
IN
OUT
PWR
PWR
LATCHED
I/O
GND
GND
PWR
IN
I/O
Pin Description
GND for XTAL
Crystal input or Reference Clock input. Nominally 25MHz.
Crystal output.
Power supply for XTAL, nominal 1.5V
VDD for REF output. nominal 1.5V.
Latch to select SMBus Address/1.5V LVCMOS copy of X1/REFIN pin
Ground pin for the REF outputs.
Ground pin for digital circuitry
1.5V digital power (dirty power)
Clock pin of SMBus circuitry, 3.3V tolerant.
Data pin for SMBus circuitry, 3.3V tolerant.
Active low input for enabling DIF pair 0. This pin has an internal pull-down.
IN
1 =disable outputs, 0 = enable outputs
OUT
Differential true clock output
OUT
Differential Complementary clock output
GND
Ground pin.
PWR
Power supply for outputs, nominally 1.5V.
Active low input for enabling DIF pair 1. This pin has an internal pull-down.
IN
1 =disable outputs, 0 = enable outputs
OUT
Differential true clock output
OUT
Differential Complementary clock output
GND
Ground pin for the PLL core.
PWR
1.5V power for the PLL core.
OUT
Differential true clock output
OUT
Differential Complementary clock output
Active low input for enabling DIF pair 2. This pin has an internal pull-down.
IN
1 =disable outputs, 0 = enable outputs
PWR
Power supply for outputs, nominally 1.5V.
GND
Ground pin.
OUT
Differential true clock output
OUT
Differential Complementary clock output
Active low input for enabling DIF pair 3. This pin has an internal pull-down.
IN
1 =disable outputs, 0 = enable outputs
GND
Ground pin.
Input notifies device to sample latched inputs and start up on first high assertion.
IN
Low enters Power Down Mode, subsequent high assertions exit Power Down
Mode. This pin has internal pull-up resistor.
Latched select input to select spread spectrum amount at initial power up :
LATCHED IN
1 = -0.5% spread, M = -0.25%, 0 = Spread Off
OCTOBER 18, 2016
3
4 O/P 1.5V PCIE GEN1-2-3 CLOCK GENERATOR
9FGU0431 DATASHEET
Test Loads
Low-Power Differential Output Test Load
5 inches
Rs
Zo=100ohm
2pF
2pF
Rs
Alternate Differential Output Terminations
Rs
Zo
Units
33
100
Ohms
27
85
REF Output Test Load
Zo = 50 ohms
33
5pF
REF Output
Alternate Terminations
Driving LVDS
3.3 Volts
R7a
Cc
R7b
Rs
Rs
Cc
Zo
R8a
R8b
LVDS CLK
Input
Driving LVDS inputs
Value
Receiver has Receiver does not
termination
have termination Note
10K ohm
140 ohm
5.6K ohm
75 ohm
0.1 uF
0.1 uF
1.2 volts
1.2 volts
Component
R7a, R7b
R8a, R8b
Cc
Vcm
4 O/P 1.5V PCIE GEN1-2-3 CLOCK GENERATOR
4
OCTOBER 18, 2016
9FGU0431 DATASHEET
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the 9FGU0431. These ratings, which are standard
values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other
conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the
recommended operating temperature range.
PARAMETER
Supply Voltage
Input Voltage
Input High Voltage, SMBus
Storage Temperature
Junction Temperature
Input ESD protection
1
2
SYMBOL
VDDxx
V
IN
V
IHSMB
Ts
Tj
ESD prot
CONDITIONS
Applies to all VDD pins
SMBus clock and data pins
MIN
-0.5
-0.5
-65
TYP
MAX
2
V
DD
+0.5V
3.3V
150
125
UNITS NOTES
V
V
V
°C
°C
V
1,2
1,3
1
1
1
1
Human Body Model
2000
Guaranteed by design and characterization, not 100% tested in production.
Operation under these conditions is neither implied nor guaranteed.
3
Not to exceed 2.5V.
Electrical Characteristics–Current Consumption
TA = T
AMB;
Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
Operating Supply Current
SYMBOL
I
DDAOP
I
DDOP
I
DDAPD
I
DDPD
I
DDAPD
I
DDPD
CONDITIONS
VDDA, All outputs active @100MHz
All VDD, except VDDA, All outputs active
@100MHz
VDDA, DIF outputs off, REF output running
All VDD, except VDDA,
DIF outputs off, REF output running
VDDA, all outputs off
All VDD, except VDDA and VDDIO, all outputs off
MIN
TYP
6.2
20
0.4
4.3
0.4
0.4
MAX UNITS NOTES
9
27
1
6.5
1
1
mA
mA
mA
mA
mA
mA
2
2
Wake-on-LAN Current
(CKPWRGD_PD# = '0'
Byte 3, bit 5 = '1')
Powerdown Current
(CKPWRGD_PD# = '0'
Byte 3, bit 5 = '0')
1
2
Guaranteed by design and characterization, not 100% tested in production.
This is the current required to have the REF output running in Wake-on-LAN mode (Byte 3, bit 5 = 1)
Electrical Characteristics–DIF Output Duty Cycle, Jitter, and Skew Characteristics
TA = T
AMB;
Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
Duty Cycle
Skew, Output to Output
Jitter, Cycle to cycle
1
SYMBOL
t
DC
t
sk3
t
jcyc-cyc
CONDITIONS
Measured differentially, PLL Mode
Averaging on, V
T
= 50%
MIN
45
TYP
50
32
16
MAX UNITS NOTES
55
50
50
%
ps
ps
1,2
1
1,2
Guaranteed by design and characterization, not 100% tested in production.
2
Measured from differential waveform
OCTOBER 18, 2016
5
4 O/P 1.5V PCIE GEN1-2-3 CLOCK GENERATOR
