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8-output 1.5V PCIe Gen1-2-3 Clock Generator

w/Zo=100ohms

9FGU0841

DATASHEET

General Description

The 9FGU0841 is a member of IDT's 1.5V Ultra-Low-Power

PCIe clock family with integrated output terminations

providing Zo=100Ω. The device has 8 output enables for clock

management, 2 different spread spectrum levels in addition to

spread off and 2 selectable SMBus addresses.

Features/Benefits

•

Direct connection to 100ohm transmission lines; saves 32

•

resistors compared to standard PCIe devices

50mW typical power consumption; reduced thermal

concerns

Outputs can optionally be supplied from any voltage

between 1.05 and 1.5V; maximum power savings

OE# pins; support DIF power management

Programmable Slew rate for each output; allows tuning for

various line length

Programmable output amplitude; allows tuning for various

application environments

DIF outputs blocked until PLL is locked; clean system

start-up

Selectable 0%, -0.25% or -0.5% spread on DIF outputs;

reduces EM

External 25MHz crystal; supports tight ppm with 0 ppm

synthesis error

Configuration can be accomplished with strapping pins;

SMBus interface not required for device control

Selectable SMBus addresses; multiple devices can easily

share an SMBus segment

3.3V tolerant SMBus interface works with legacy controllers

Space saving 48-pin 6x6 mm VFQFPN; minimal board

space

Recommended Application

•

1.5V PCIe Gen1-2-3 Clock Generator

Output Features

•

8 - 100MHz Low-Power (LP) HCSL DIF pairs

•

w/Zo=100ohms

1 - 1.5V LVCMOS REF output w/Wake-On-LAN (WOL)

support

Key Specification

•

DIF cycle-to-cycle jitter <50ps

DIF output-to-output skew < 60ps

DIF phase jitter is PCIe Gen1-2-3 compliant

REF phase jitter is < 3.0ps RMS

Functional Block Diagram

vOE(7:0)#

REF1.5

XIN/CLKIN_25

OSC

DIF7

DIF6

DIF5

SS Capable PLL

vSADR

vSS_EN_tri

^CKPWRGD_PD#

SDATA_3.3

SCLK_3.3

CONTROL

LOGIC

DIF4

DIF3

DIF2

DIF1

DIF0

9FGU0841 OCTOBER 18, 2016

9FGU0841 DATASHEET

Pin Configuration

^CKPWRGD_PD#

VDD1.5

VDDIO

vOE7#

vOE6#

48 47 46 45 44 43 42 41 40 39 38 37

vSS_EN_tri

GNDXTAL

XIN/CLKIN_25

VDDXTAL1.5

VDDREF1.5

vSADR/REF1.5

GNDREF

GNDDIG

SCLK_3.3

SDATA_3.3

VDDDIG1.5

vOE0#

DIF0

VDDIO

GND

DIF2#

DIF2

DIF5#

DIF5

vOE4#

DIF4#

DIF4

VDDIO

VDDA1.5

GNDA

vOE3#

DIF3#

DIF3

vOE2#

9FGU0841

13 14 15 16 17 18 19 20 21 22 23 24

DIF0#

vOE1#

DIF1#

DIF1

VDD1.5

VDDIO

48-pin MLF, 6x6 mm, 0.4mm pitch

vv prefix indicates internal 60KOhm pull down resistor

v prefix indicates internal 120KOhm pull down resistor

^ prefix indicates internal 120KOhm pull up resistor

Power Management Table

SMBus

DIFx

REF

OEx#

True O/P

Comp. O/P

OE bit

Low

Hi-Z

Running

Running Running

Low

1. REF is Hi-Z until the 1st assertion of CKPWRGD_PD# high. After this, when

CKPWRGD_PD# is low, REF is Low.

CKPWRGD_PD#

SMBus Address Selection Table

State of SADR on first application

of CKPWRGD_PD#

SADR

Address

1101000

1101010

Read/Write Bit

Power Connections

Pin Number

VDD

20,38

13,21,31,39,

VDDIO

GND

22,29,40

Description

XTAL OSC

REF Power

Digital (dirty)

Power

DIF outputs

PLL Analog

8-OUTPUT 1.5V PCIE GEN1-2-3 CLOCK GENERATOR W/ZO=100OHMS

vOE5#

DIF7#

DIF6#

GND

DIF7

DIF6

OCTOBER 18, 2016

9FGU0841 DATASHEET

Pin Descriptions

PIN #

PIN NAME

vSS_EN_tri

GNDXTAL

XIN/CLKIN_25

VDDXTAL1.5

VDDREF1.5

vSADR/REF1.5

GNDREF

GNDDIG

SCLK_3.3

SDATA_3.3

VDDDIG1.5

VDDIO

vOE0#

DIF0

DIF0#

vOE1#

DIF1

DIF1#

VDD1.5

VDDIO

GND

DIF2

DIF2#

vOE2#

DIF3

DIF3#

vOE3#

GNDA

VDDA1.5

VDDIO

DIF4

DIF4#

vOE4#

DIF5

DIF5#

vOE5#

VDD1.5

VDDIO

TYPE

LATCHED

GND

OUT

PWR

LATCHED

I/O

GND

I/O

PWR

OUT

PWR

GND

OUT

GND

PWR

OUT

PWR

DESCRIPTION

Latched select input to select spread spectrum amount at initial power up :

1 = -0.5% spread, M = -0.25%, 0 = Spread Off

GND for XTAL

Crystal input or Reference Clock input. Nominally 25MHz.

Crystal output.

Power supply for XTAL, nominal 1.5V

VDD for REF output. nominal 1.5V.

Latch to select SMBus Address/1.5V LVCMOS copy of X1/REFIN pin

Ground pin for the REF outputs.

Ground pin for digital circuitry

Clock pin of SMBus circuitry, 3.3V tolerant.

Data pin for SMBus circuitry, 3.3V tolerant.

1.5V digital power (dirty power)

Power supply for differential outputs

Active low input for enabling DIF pair 0. This pin has an internal pull-down.

1 =disable outputs, 0 = enable outputs

Differential true clock output

Differential Complementary clock output

Active low input for enabling DIF pair 1. This pin has an internal pull-down.

1 =disable outputs, 0 = enable outputs

Differential true clock output

Differential Complementary clock output

Power supply, nominally 1.5V

Power supply for differential outputs

Ground pin.

Differential true clock output

Differential Complementary clock output

Active low input for enabling DIF pair 2. This pin has an internal pull-down.

1 =disable outputs, 0 = enable outputs

Differential true clock output

Differential Complementary clock output

Active low input for enabling DIF pair 3. This pin has an internal pull-down.

1 =disable outputs, 0 = enable outputs

Ground pin for the PLL core.

1.5V power for the PLL core.

Power supply for differential outputs

Differential true clock output

Differential Complementary clock output

Active low input for enabling DIF pair 4. This pin has an internal pull-down.

1 =disable outputs, 0 = enable outputs

Differential true clock output

Differential Complementary clock output

Active low input for enabling DIF pair 5. This pin has an internal pull-down.

1 =disable outputs, 0 = enable outputs

Power supply, nominally 1.5V

Power supply for differential outputs

OCTOBER 18, 2016

8-OUTPUT 1.5V PCIE GEN1-2-3 CLOCK GENERATOR W/ZO=100OHMS

9FGU0841 DATASHEET

Pin Descriptions (cont.)

PIN #

PIN NAME

40 GND

41 DIF6

42 DIF6#

vOE6#

DIF7

DIF7#

vOE7#

VDDIO

^CKPWRGD_PD#

TYPE

GND

OUT

PWR

DESCRIPTION

Ground pin.

Differential true clock output

Differential Complementary clock output

Active low input for enabling DIF pair 6. This pin has an internal pull-down.

1 =disable outputs, 0 = enable outputs

Differential true clock output

Differential Complementary clock output

Active low input for enabling DIF pair 7. This pin has an internal pull-down.

1 =disable outputs, 0 = enable outputs

Power supply for differential outputs

Input notifies device to sample latched inputs and start up on first high

assertion. Low enters Power Down Mode, subsequent high assertions exit

Power Down Mode. This pin has internal pull-up resistor.

8-OUTPUT 1.5V PCIE GEN1-2-3 CLOCK GENERATOR W/ZO=100OHMS

OCTOBER 18, 2016

9FGU0841 DATASHEET

Test Loads

Low-Power HCSL Differential Output Test Load

5 inches

Zo=100ohm

2pF

Device

REF Output Test Load

Zo = 50 ohms

5pF

Device

Alternate Terminations

3.3V

Driving LVDS

R7a

R7b

Device

R8a

R8b

LVDS Clock

input

Driving LVDS inputs

Value

Receiver has Receiver does not

termination

have termination Note

10K ohm

140 ohm

5.6K ohm

75 ohm

0.1 uF

1.2 volts

Component

R7a, R7b

R8a, R8b

Vcm

OCTOBER 18, 2016

8-OUTPUT 1.5V PCIE GEN1-2-3 CLOCK GENERATOR W/ZO=100OHMS