DATASHEET
2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR
9FGV0241
Description
The 9FGV0241 is a 2-output very low power frequency
generator for PCIe Gen 1, 2, 3 and 4 applications with
integrated output terminations providing Zo = 100. The
device has 2 output enables for clock management and
supports 2 different spread spectrum levels in addition to
spread off.
Features/Benefits
•
Integrated terminations provide 100 differential Zo;
•
•
•
•
•
•
•
•
•
•
•
reduced component count and board space
1.8V operation; reduced power consumption
OE# pins; support DIF power management
LP-HCSL differential clock outputs; reduced power and
board space
Programmable Slew rate for each output; allows tuning
for various line lengths
Programmable output amplitude; allows tuning for
various application environments
DIF outputs blocked until PLL is locked; clean system
start-up
Selectable 0%, -0.25% or -0.5% spread on DIF outputs;
reduces EMI
External 25MHz crystal; supports tight ppm with 0 ppm
synthesis error
Configuration can be accomplished with strapping pins;
SMBus interface not required for device control
3.3V tolerant SMBus interface works with legacy
controllers
Space saving 4 x 4 mm 24-VFQFPN; minimal board
space
Recommended Application
PCIe Gen1-4 clock generation for Riser Cards, Storage,
Networking, JBOD, Communications, Access Points
Output Features
•
2 – 0.7V low-power HCSL-compatible (LP-HCSL) DIF
•
pairs with Zo = 100
1 – 1.8V LVCMOS REF output w/Wake-On-LAN (WOL)
support
Key Specifications
•
•
•
•
DIF cycle-to-cycle jitter <50ps
DIF output-to-output skew <50ps
DIF phase jitter is PCIe Gen1-2-3-4 compliant
REF phase jitter is < 1.5ps RMS
Block Diagram
vOE(1:0)#
XIN/CLKIN_25
IDT 603-25-150JA4C or
603-25-150JA4I 25MHz
2
REF
X2
SSC Capable
PLL
vSADR
vSS_EN_tri
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
DIF1
DIF0
Control
Logic
IDT®
2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR
1
9FGV0241
JUNE 6, 2019
9FGV0241
2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR
Pin Configuration
^CKPWRGD_PD#
vSS_EN_tri
GNDXTAL
VDD1.8
VDD1.8
24 23 22 21 20 19
X1_25 1
X2 2
VDDXTAL1.8 3
vSADR/REF1.8 4
GNDREF 5
GNDDIG 6
vOE1#
18 DIF1#
17 DIF1
16 VDDA1.8
15 GNDA
14 DIF0#
13 DIF0
vOE0#
2
9FGV0241
connect
epad to GND
7
VDDDIG1.8
8
SCLK_3.3
9 10 11 12
SDATA_3.3
+
24-pin VFQFPN, 4x4 mm, 0.5mm pitch
^ prefix indicates internal 120KOhm pull up resistor
v prefix indicates internal 120KOhm pull down resistor
SMBus Address Selection Table
State of SADR on first application
of CKPWRGD_PD#
SADR
0
1
Address
1101000
1101010
Read/Write Bit
x
x
Power Management Table
SMBus
DIFx
REF
OE bit
True O/P
Comp. O/P
0
X
Low
Low
Hi-Z
1
1
1
Running
Running
Running
1
0
Low
Low
Low
1. REF is Hi-Z until the 1st assertion of CKPWRGD_PD# high. After this,
when CKPWRG_PD# is low, REF is Low.
CKPWRGD_PD#
Power Connections
Pin Number
VDD
3
7
11,20
16
GND
5,24
6
10,21
15
Description
XTAL, REF
Digital Power
DIF outputs
PLL Analog
IDT®
2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR
GND
GND
9FGV0241
JUNE 6, 2019
9FGV0241
2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR
Pin Descriptions
Pin# Pin Name
1
X1_25
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
X2
VDDXTAL1.8
vSADR/REF1.8
GNDREF
GNDDIG
VDDDIG1.8
SCLK_3.3
SDATA_3.3
GND
VDD1.8
vOE0#
DIF0
DIF0#
GNDA
VDDA1.8
DIF1
DIF1#
vOE1#
VDD1.8
GND
^CKPWRGD_PD#
vSS_EN_tri
GNDXTAL
Type
IN
OUT
PWR
LATCHED
I/O
GND
GND
PWR
IN
I/O
GND
PWR
Pin Description
Crystal input, Nominally 25.00MHz.
Crystal output.
Power supply for XTAL, nominal 1.8V
Latch to select SMBus Address/1.8V LVCMOS copy of X1 pin.
Ground pin for the REF outputs.
Ground pin for digital circuitry
1.8V digital power (dirty power)
Clock pin of SMBus circuitry, 3.3V tolerant.
Data pin for SMBus circuitry, 3.3V tolerant.
Ground pin.
Power supply, nominal 1.8V
Active low input for enabling DIF pair 0. This pin has an internal pull-down.
IN
1 =disable outputs, 0 = enable outputs
OUT
Differential true clock output
OUT
Differential Complementary clock output
GND
Ground pin for the PLL core.
PWR
1.8V power for the PLL core.
OUT
Differential true clock output
OUT
Differential Complementary clock output
Active low input for enabling DIF pair 1. This pin has an internal pull-down.
IN
1 =disable outputs, 0 = enable outputs
PWR
Power supply, nominal 1.8V
GND
Ground pin.
Input notifies device to sample latched inputs and start up on first high assertion.
IN
Low enters Power Down Mode, subsequent high assertions exit Power Down
Mode. This pin has internal pull-up resistor.
Latched select input to select spread spectrum amount at initial power up :
LATCHED IN
1 = -0.5% spread, M = -0.25%, 0 = Spread Off
GND
GND for XTAL
IDT®
2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR
3
9FGV0241
JUNE 6, 2019
9FGV0241
2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR
Test Loads
Low-Power HCSL Differential Output Test Load
5 inches
Rs
Zo=100ohm
2pF
2pF
Rs
Device
REF Output Test Load
Zo = 50 ohms
33
5pF
REF Output
Alternate Terminations
3.3V
Driving LVDS
Cc
R7a
R7b
Rs
Zo
Cc
Rs
Device
R8a
R8b
LVDS Clock
input
Driving LVDS inputs with the 9FGV0241
Value
Receiver has Receiver does not
Component
termination
have termination Note
R7a, R7b
10K ohm
140 ohm
R8a, R8b
5.6K ohm
75 ohm
Cc
0.1 uF
0.1 uF
Vcm
1.2 volts
1.2 volts
IDT®
2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR
4
9FGV0241
JUNE 6, 2019
9FGV0241
2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the 9FGV0241. These ratings, which are standard
values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other
conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over
the recommended operating temperature range.
PARAMETER
1.8V Supply Voltage
Input Voltage
Input High Voltage, SMBus
Storage Temperature
Junction Temperature
Input ESD protection
1
2
SYMBOL
VDDxx
V
IN
V
IHSMB
Ts
Tj
ESD prot
CONDITIONS
Applies to All VDD pins
SMBus clock and data pins
MIN
-0.5
-0.5
-65
TYP
MAX
2.5
V
DD
+0.3V
3.6V
150
125
UNITS NOTES
V
V
V
°C
°C
V
1,2
1, 3
1
1
1
1
Human Body Model
2000
Guaranteed by design and characterization, not 100% tested in production.
Operation under these conditions is neither implied nor guaranteed.
3
Not to exceed 2.5V.
Electrical Characteristics–Current Consumption
TA = T
COM
or T
IND;
Supply Voltage per VDD of normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
Operating Supply Current
Suspend Supply Current
Powerdown Current
1
2
SYMBOL
I
DDAOP
I
DDOP
I
DDSUSP
I
DDPD
CONDITIONS
VDDA, PLL Mode, All outputs active @100MHz
VDD, All outputs active @100MHz
VDDxxx, PD# = 0, Wake-On-LAN enabled
PD#=0
MIN
TYP
7
15
6
0.6
MAX
8
18
8
1
UNITS
mA
mA
mA
mA
NOTES
1
1
1
1, 2
Guaranteed by design and characterization, not 100% tested in production.
Assuming REF is not running in power down state
Electrical Characteristics–Output Duty Cycle, Jitter, and Skew Characteristics
TA = T
COM
or T
IND;
Supply Voltage per VDD of normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
Duty Cycle
Skew, Output to Output
Jitter, Cycle to cycle
1
2
SYMBOL
t
DC
t
sk3
t
jcyc-cyc
CONDITIONS
Measured differentially, PLL Mode
V
T
= 50%
PLL mode
MIN
45
TYP
50
34
14
MAX
55
50
50
UNITS
%
ps
ps
NOTES
1
1
1,2
Guaranteed by design and characterization, not 100% tested in production.
Measured from differential waveform
IDT®
2-OUTPUT VERY LOW POWER PCIE GEN 1-2-3-4 CLOCK GENERATOR
5
9FGV0241
JUNE 6, 2019
