DATASHEET
56-pin CK505 for Intel Desktop Systems
Recommended Application:
CK505 clock, 56-pin Intel Yellow Cover part
Output Features:
•
2 - CPU differential low power push-pull pairs
•
7- SRC differential low power push-pull pairs
•
1 - CPU/SRC selectable differential low power push-pull pair
•
1 - SRC/DOT selectable differential low power push-pull pair
•
5 - PCI, 33MHz
•
1 - PCI_F, 33MHz free running
•
1 - USB, 48MHz
•
1 - REF, 14.318MHz
Key Specifications:
•
CPU outputs cycle-cycle jitter < 85ps
•
SRC output cycle-cycle jitter < 125ps
•
PCI outputs cycle-cycle jitter < 250ps
•
+/- 100ppm frequency accuracy on all outputs
•
SRC are PCIe Gen2 compliant
ICS9LP525-2
Features/Benefits:
•
Supports spread spectrum modulation, default is 0.5%
down spread
•
Uses external 14.318MHz crystal, external crystal load
caps are required for frequency tuning
•
Selectable SRC differential push-pull pair/two single
ended outputs
Table 1: CPU Frequency Select Table
FS
L
C
B0b7
0
0
0
0
1
1
1
1
2
FS
L
B
B0b6
0
0
1
1
0
0
1
1
1
FS
L
A
B0b5
0
1
0
1
0
1
0
1
1
CPU
MHz
266.66
133.33
200.00
166.66
333.33
100.00
400.00
SRC
MHz
PCI
MHz
REF
MHz
USB DOT
MHz MHz
100.00
33.33 14.318 48.00 96.00
Reserved
1. FS
L
A and FS
L
B are low-threshold inputs.Please see V
IL_FS
and V
IH_FS
specifications in
the Input/Supply/Common Output Parameters Table for correct values.
Also refer to the Test Clarification Table.
2. FS
L
C is a three-level input. Please see the V
IL_FS
and V
IH_FS
specifications in the Input/Supply/Common Output Parameters Table for correct values.
Pin Configuration
PCI0/CR#_A 1
VDDPCI 2
PCI1/CR#_B
PCI2/TME
PCI3/CFG0
PCI4/SRC5_EN
PCI_F5/ITP_EN
GNDPCI
VDD48
USB_48MHz/FSLA
GND48
VDD96_IO
DOTT_96/SRCT0
DOTC_96/SRCC0
GND
VDD
SRCT1/SE1
SRCC1/SE2
GND
VDDPLL3_IO
SRCT2/SATAT
SRCC2/SATAC
GNDSRC
SRCT3/CR#_C
SRCC3/CR#_D
VDDSRC_IO
SRCT4
SRCC4
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56 SCLK
55 SDATA
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
REF0/FSLC/TEST_SEL
VDDREF
X1
X2
GNDREF
FSLB/TEST_MODE
CK_PWRGD/PD#
VDDCPU
CPUT0
CPUC0
GNDCPU
CPUT1_F
CPUC1_F
VDDCPU_IO
VOUT
CPUT2_ITP/SRCT8
CPUC2_ITP/SRCC8
VDDSRC_IO
SRCT7/CR#_F
SRCC7/CR#_E
GNDSRC
SRCT6
SRCC6
VDDSRC
PCI_STOP#/SRCT5
CPU_STOP#/SRCC5
56-SSOP & TSSOP
IDT
PC MAIN CLOCK
®
9LP525-2
1397—11/08/10
1
ICS9LP525-2
PC MAIN CLOCK
Pin Description
PIN #
PIN NAME
TYPE
DESCRIPTION
3.3V PCI clock output or Clock Request control A for either SRC0 or SRC2 pair
The power-up default is PCI0 output, but this pin may also be used as a Clock Request control of SRC pair 0 or SRC pair 2 via
SMBus. Before configuring this pin as a Clock Request Pin, the PCI output must first be disabled in byte 2, bit 0 of SMBus address
space . After the PCI output is disabled (high-Z), the pin can then be set to serve as a Clock Request pin for either SRC pair 2 or
pair 0 using the CRA#_EN bit located in byte 5 of SMBUs address space.
Byte 5, bit 7
0 = PCI0 enabled (default)
1= CRA# enabled. Byte 5, bit 6 controls whether CRA# controls SRC0 or SRC2 pair
Byte 5, bit 6
0 = CRA# controls SRC0 pair (default),
1= CRA# controls SRC2 pair
Power supply for PCI clocks, nominal 3.3V
3.3V PCI clock output/Clock Request control B for either SRC1 or SRC4 pair
The power-up default is PCI1 output, but this pin may also be used as a Clock Request control of SRC pair 1 or SRC pair 4 via
SMBus. Before configuring this pin as a Clock Request Pin, the PCI output must first be disabled in byte 2, bit 1 of SMBus address
space . After the PCI output is disabled (high-Z), the pin can then be set to serve as a Clock Request pin for either SRC pair 1 or
pair 4 using the CRB#_EN bit located in byte 5 of SMBUs address space.
Byte 5, bit 5
0 = PCI1 enabled (default)
1= CRB# enabled. Byte 5, bit 6 controls whether CRB# controls SRC1 or SRC4 pair
Byte 5, bit 4
0 = CRB# controls SRC1 pair (default)
1= CRB# controls SRC4 pair
3.3V PCI clock output / Trusted Mode Enable(TME) Latched Input. This pin is sampled on power-up as follows
0=Overclocking of CPU and SRC allowed
1=Overclocking of CPU and SRC NOT allowed
After being sampled on power-up, this pin becomes a 3.3V PCI Output
3.3V PCI clock output/Configuration Strap. See PCI3 Configuration Table for more information
3.3V PCI clock output / SRC5 pair or PCI_STOP#/CPU_STOP# enable strap. On powerup, the logic value on this pin determines if
the SRC5 pair is enabled or if CPU_STOP#/PCI_STOP# is enabled (pins 29 and 30). The latched value controls the pin function on
pins 29 and 30 as follows
0 = PCI_STOP#/CPU_STOP#
1 = SRC5/SRC5#
Free running PCI clock output and ITP/SRC8 enable strap. This output is not affected by the state of the PCI_STOP# pin. On
powerup, the state of this pin determines whether pins 38 and 39 are an ITP or SRC pair.
0 =SRC8/SRC8#
1 = ITP/ITP#
Ground pin for the PCI outputs
Power pin for the 48MHz output and PLL.3.3V
3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values. / Fixed
48MHz USB clock output. 3.3V.
Ground pin for the 48MHz outputs
Power supply for DOT96 clocks, nominal 0.8V from source/emitter of external pass transistor.
True clock of low power differential SRC or DOT96. The power-up default function is SRC0. After powerup, this pin function may be
changed to DOT96 via SMBus Byte 1, bit 7 as follows:
0= SRC0
1=DOT96
Complement clock of low power differential SRC or DOT96. The power-up default function is SRC0#. After powerup, this pin
function may be changed to DOT96# via SMBus Byte 1, bit 7 as follows
0= SRC0#
1=DOT96#
Ground pin.
Power supply, nominal 3.3V
True clock of low power differential SRC1 clock pair / 3.3V single-ended output. The powerup default is 100 MHz SRC, -0.5%
downspread. The pin function may be changed via SMBus B1b[4:1]
Complement clock of push-pull differential SRC1 clock pair / 3.3V single-ended output. The powerup default is 100 MHz SRC, -
0.5% downspread. The pin function may be changed via SMBus B1b[4:1]
Ground pin.
Power supply for PLL3. 0.8V nominal from source/emitter of external pass transistor
True clock of low power differentiall SRC/SATA clock pair.
Complement clock of differential push-pull SRC/SATA clock pair.
Ground pin for the SRC outputs
1
PCI0/CR#_A
I/O
2
VDDPCI
PWR
3
PCI1/CR#_B
I/O
4
5
PCI2/TME
PCI3/CFG0
I/O
I/O
6
PCI4/SRC5_EN
I/O
7
8
9
10
11
12
13
PCI_F5/ITP_EN
GNDPCI
VDD48
USB_48MHz/FSLA
GND48
VDD96_IO
DOTT_96/SRCT0
I/O
PWR
PWR
I/O
PWR
PWR
OUT
14
15
16
17
18
19
20
21
22
23
DOTC_96/SRCC0
GND
VDD
SRCT1/SE1
SRCC1/SE2
GND
VDDPLL3_IO
SRCT2/SATAT
SRCC2/SATAC
GNDSRC
OUT
PWR
PWR
OUT
OUT
PWR
PWR
OUT
OUT
PWR
IDT
TM
/ICS
TM
PC MAIN CLOCK
1397—11/08/10
2
ICS9LP525-2
PC MAIN CLOCK
Pin Description (continued)
PIN #
PIN N A ME
TYPE
D ESC R IPTION
Complementary cloc k of differential SRC clock pair/ Clock Reques t control D for either SRC1 or SRC4 pair
The power-up default is SRCCLK3 output, but this pin may als o be used as a Clock Request control of SRC pair 1 or SRC pair 4
via SMBus. Before configuring this pin as a Cloc k Request Pin, the SRC output must first be disabled in byte 4, bit 7 of SMBus
addres s s pace . After the SRC output is disabled, the pin c an then be set to serve as a Clock Request pin for either SRC pair 1 or
pair 4 using the CRD#_EN bit located in byte 5 of SMBUs address space.
By te 5, bit 1
0 = SRC3 enabled (default)
1= CRD# enabled. By te 5, bit 0 controls whether CRD# controls SRC1 or SRC4 pair
Byte 5, bit 0
0 = CRD# controls SRC1 pair (default),
1= CRD# c ontrols SRC4 pair
Power supply for SRC clocks. 0.8V nominal from source/emitter of external pass transis tor
True clock of low power differential SRC cloc k pair.
Complement clock of low power differential SRC clock pair.
Ref, XTAL power supply, nominal 3.3V
Stops all PCICLKs at logic 0 level, when low. F ree running PCICLKs are not effected by this input. / T rue clock of differential push-
pull SRC pair.
Supply for SRC PLL, 3.3V nominal
Complement clock of low power differential SRC clock pair.
True clock of low power differential SRC cloc k pair.
G round pin for the SRC outputs
Complement clock of differential push-pull SRC clock pair. / Clock Request c ontrol E for SRC6 pair. T he power-up default is
SRC7#, but this pin may also be used as a Clock Reques t control of SRC6 v ia SMBus . Before configuring this pin as a Clock
Request Pin, the SRC7 output pair must first be disabled in byte 3, bit 3 of SMBus configuration space . After the SRC output is
disabled (high-Z), the pin can then be set to serve as a Clock Request for SRC6 pair using byte 6, bit 7 of SMBus configuration
space
By te 6, bit 7
0 = SRC7# enabled (default)
1= CRE# enabled.
True clock of differential push-pull SRC cloc k pair/ Clock Reques t control 8 for SRC8 pair
The power-up default is SRC7, but this pin may also be used as a Clock Request control of SRC8 via SMBus. Before c onfiguring
this pin as a Clock Request Pin, the SRC7 output pair must first be disabled in by te 3, bit 3 of SMBus configuration s pace After the
SRC output is disabled (high-Z), the pin can then be set to serve as a Cloc k Request for SRC8 pair using by te 6, bit 6 of SMBus
configuration space.
By te 6, bit 6
0 = SRC7# enabled (default)
1 = CRF# enabled.
Power supply for SRC clocks. 0.8V nominal from source/emitter of external pass transis tor
Complement clock of low power differential CPU2/Complement clock of differential SRC pair. The function of this pin is determined
by the latched input value on pin 7, PCIF5/ITP_EN on powerup. T he function is as follows:
Pin 7 latc hed input Value
0 = SRC8#
1 = ITP#
True clock of low power differential CPU2/True clock of differential SRC pair. The function of this pin is determined by the latched
input value on pin 7, PCIF5/ITP_EN on powerup. T he function is as follows:
Pin 7 latc hed input Value
0 = SRC8
1 = ITP
O P Amp comparator output. T his pin drives the base/gate of the ex ternal pass trans istor
Supply for CPU clocks . 0.8V nominal from s ource/emitter of external pass trans istor
Complementary cloc k of low power differential pus h-pull CPU output. This CPU clock is free running during iAMT.
True clock of differential push-pull CPU cloc k pair. T his clock is free running during iAMT.
G round pin for the CPU outputs
Complement clock of low power differential CPU clock pair.
True clock of low power differential CPU cloc k pair.
Supply for CPU PLL, 3.3V nominal
Notifies CK505 to sample latched inputs , or iAMT entry/exit, or PWRDWN# mode
3.3V tolerant input for CPU frequency selection. Refer to input elec tric al characteristic s for Vil_FS and Vih_F S values.
TEST_MO DE is a real time input to select between Hi-Z and REF /N divider mode while in test mode. Refer to Test Clarification
Table.
G round pin for the REF outputs.
Cry stal output, Nominally 14.318MHz
Cry stal input, Nominally 14.318MHz.
Ref, XTAL power supply, nominal 3.3V
14.318 MHz reference clock./ 3.3V tolerant input for CPU frequency selection. Refer to input electrical charac teristics for Vil_F S
and Vih_F S values. /TEST_Sel: 3-level latc hed input to enable test mode. Refer to Tes t Clarification T able
Data pin for SMBus circ uitry , 5V tolerant.
Clock pin of SMBus circuitry, 5V tolerant.
25
SRCC3/CR#_D
I/O
26
27
28
29
30
31
32
33
34
VDDSRC_IO
SRCT4
SRCC4
CPU_ST O P#/SRCC5
PCI_ST O P#/SRCT 5
VDDSRC
SRCC6
SRCT6
G NDSRC
PWR
O UT
O UT
I/O
I/O
PWR
O UT
O UT
PWR
35
SRCC7/CR#_E
I/O
36
SRCT7/CR#_F
I/O
37
VDDSRC_IO
PWR
38
CPUC2_IT P/SRCC8
O UT
39
CPUT2_IT P/SRCT8
O UT
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
VO UT
VDDCPU_IO
CPUC1_F
CPUT1_F
G NDCPU
CPUC0
CPUT0
VDDCPU
CK_PWRG D/PD#
F SLB/T EST _MO DE
G NDREF
X2
X1
VDDREF
REF 0/F SLC/TEST_SEL
SDATA
SCLK
PWR
PWR
O UT
O UT
PWR
O UT
O UT
PWR
IN
IN
PWR
O UT
IN
PWR
I/O
I/O
IN
IDT
TM
/ICS
TM
PC MAIN CLOCK
1397—11/08/10
3
ICS9LP525-2
PC MAIN CLOCK
General Description
ICS9LP525-2
is compliant Intel CK505 Yellow Cover specification. This clock synthesizer provides a single chip solution for Intel desktop
chipsets.
ICS9LP525-2
is driven with a 14.318MHz crystal. It also provides a tight ppm accuracy output for Serial ATA and PCI-Express
support.
Block Diagram
X1
X2
REF
REF
CPU(1:0)
OSC
SRC8/ITP
CPU
CPU PLL1
SS
SRC
SRC_MAIN
SRC(7:3)
PCI33MHz
SRC
PCI(5:0)
PCI33MHz
PLL3
SS
SRC2/SATA
FSLA
CKPWRGD/PD#
PCI_STOP#
CPU_STOP#
CR#_(A:F)
SRC5_EN
ITP_EN
FSLC/TESTSEL
FSLB/TESTMODE
SRC1/SE(2:1)
Control
Logic
Differential Output
SE Outputs
7
SATA
SRC0/DOT96
PLL2
Non-SS
DOT96MHz
48MHz
48MHz
Power Groups
Pin Number
VDD
GND
41, 47
44
16
15
26, 31, 37
20
12
9
53
2
23, 34
19
11
11
50
8
Description
CPUCLK
Master Clock, Analog
SRCCLK
PLL3/SE
DOT 96Mhz
USB 48
Xtal, REF
PCICLK
IDT
TM
/ICS
TM
PC MAIN CLOCK
1397—11/08/10
4
ICS9LP525-2
PC MAIN CLOCK
External Pass Transistor Connection for Desktop Applications
ICS9LP525-2
VDDCPU_IO, Pin 41
3.3V
R=15
3.3V
CPU_IO Decoupling
Network
-
+
Vref
VOUT
PIN 40
2N3904
R=33
96_IO Decoupling
Network
C=100pF
VD D _IO
0. 8V N OM .
C >= 40uF
PLL3_IO Decoupling
Network
SRC_IO Decoupling
Network
VDDSRC_IO Pin 37, 26
VDDPLL3_IO, Pin 20
VDD96_IO, Pin 12
IDT
TM
/ICS
TM
PC MAIN CLOCK
1397—11/08/10
5
