9LPR363
Datasheet
Low Power Programmable Timing Control Hub™ for P4™ processor
Key Specifications:
•
CPU outputs cycle-cycle jitter < 85ps
•
PCIEX outputs cycle-cycle jitter < 125ps
Output Features:
•
SATA outputs cycle-cycle jitter < 125ps
•
2 - 0.8V push-pull differential CPU pairs
•
PCI outputs cycle-cycle jitter < 500ps
•
7 - 0.8V push-pull differential PCIEX pairs
•
+/- 100ppm frequency accuracy on CPU, PCIEX and
SATA clocks
•
1 - 0.8V push-pull differential SATA pair
+/- 100ppm frequency accuracy on USB clocks
•
1 - 0.8V push-pull differential CPU/PCIEX selectable pair •
•
1 - 0.8V push-pull differential 27MHz/LCDCLK/PCIEX
selectable pair
Features/Benefits:
•
4 - PCI (33MHz)
•
Supports tight ppm accuracy clocks for Serial-ATA and
PCIEX
•
2 - PCICLK_F, (33MHz) free-running
•
Supports programmable spread percentage and
•
1 - USB, 48MHz
frequency
•
1 - DOT96/PCIEX selectable pair
•
Uses external 14.318MHz crystal, external crystal load
•
2 - REF, 14.318MHz
caps are required for frequency tuning
•
PEREQ# pins to support PCIEX power management.
•
Low power differential clock outputs (No 50Ω resistor
to GND needed)
•
iAMT support
Recommended Application:
Low Power CK505 Compliant Main Clock
Pin Configuration
VDDPCI
GND
PCICLK1
PCICLK2
*SELPCIEX0_LCD#/PCICLK3
GND
VDDPCI
ITP_EN/PCICLK_F4
*SELLCD_27#/PCICLK_F5
VttPWR_GD/PD#
VDD48
FS
L
A/USB_48MHz
GND
PCIeT_L9/DOTT_96MHzL
PCIeC_L9/DOTC_96MHzL
FS
L
B/TEST_MODE
27FIX/LCD_SSCGT/PCIeT_L0
27SS/LCD_SSCGC/PCIeC_L0
PCIeT_L1
PCIeC_L1
VDDPCIEX
PCIeT_L2
PCIeC_L2
PCIeT_L3
PCIeC_L3
SATACLKT_L
SATACLKC_L
VDDPCIEX
GND
PCIeT_L4
PCIeC_L4
*PEREQ3#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
Latch Select Table
PCICLK0/REQ_SEL**
PCI/PCIEX_STOP#
CPU_STOP#
REF1/FSLC/TEST_SEL
REF0
GND
X1
X2
VDDREF
SDATA
SCLK
GND
Pin5
Pin9
Pin14/15
PCIEX9
DOT96
PCIEX9
DOT96
Pin17/18
27FIX/SS
LCD
PCIEX0
PCIEX0
SELPCIEX0_LCD#/ SELLCD_27#=0
SELLCD_27#=1
PCI3 = 0 (low)
SELPCIEX0_LCD#/ SELLCD_27#=0
PCI3 = 1 (high)
SELLCD_27#=1
Functionality Table
FS
L
C
0
0
0
0
1
1
1
1
ICS9LPR363
CPUT_L0
CPUC_L0
VDDCPU
FS
L
B
0
0
1
1
0
0
1
1
FS
L
A
0
1
0
1
0
1
0
1
CPUT_L1F
CPUC_L1F
VREF
GNDA
VDDA
CPUITPT_L2/PCIeT_L8
CPUITPC_L2/PCIeC_L8
VDDPCIEX
PEREQ1#/PCIeT_L7
PEREQ2#/PCIeC_L7
CPU
PCI MHz
MHz
33.33
266.66
33.33
133.33
33.33
200.00
33.33
166.66
33.33
333.33
33.33
100.00
33.33
400.00
200.00
33.33
PCIEX
MHz
100.00
100.00
100.00
100.00
100.00
100.00
100.00
100.00
Spread %
0.5% Down
0.5% Down
0.5% Down
0.5% Down
0.5% Down
0.5% Down
0.5% Down
0.5% Down
PCIeT_L6
PCIeC_L6
GND
36
PCIeT_L5
35
PCIeC_L5
34
PWRSAVE#*
33
PEREQ4#*
64-TSSOP
* Internal Pull-Up Resistor
** Internal Pull-Down Resistor
Note: Please add an external resistor for pull up or down,
never rely on an internal resistor when the pin is connected to a device
1199–08/20/08
9LPR363
Datasheet
Pin Description
PIN #
1
2
3
4
5
6
7
8
PIN NAME
VDDPCI
GND
PCICLK1
PCICLK2
*SELPCIEX0_LCD#/PCICLK3
GND
VDDPCI
ITP_EN/PCICLK_F4
TYPE
PWR
PWR
OUT
OUT
#N/A
PWR
PWR
I/O
DESCRIPTION
Power supply for PCI clocks, nominal 3.3V
Ground pin.
PCI clock output.
PCI clock output.
#N/A
Ground pin.
Power supply for PCI clocks, nominal 3.3V
Free running PCI clock not affected by PCI_STOP#.
ITP_EN: latched input to select CPU_ITP/SRC output functionality
1 = CPU_ITP pair
0 = SRC pair
Free running PCI clock not affected by PCI_STOP#.
SELLCD_27#: latched input to select pin functionality. See Latch Select Table
This 3.3V LVTTL input is a level sensitive strobe used to determine when latch inputs are valid
and are ready to be sampled. This is an active high input. / Asynchronous active low input pin
used to power down the device into a low power state.
Power pin for the 48MHz output.3.3V
3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for
Vil_FS and Vih_FS values. / Fixed 48MHz USB clock output. 3.3V.
Ground pin.
True clock of 0.8V differential push-pull PCI_Express pair / True clock of differential DOT96
output pair. (no 50ohm resistor to GND needed)
Complement clock of 0.8V differential push-pull PCI_Express pair. / Complement clock of
differential DOT96 push-pull output . (no 50ohm resistor to GND needed)
3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for
Vil_FS and Vih_FS values. TEST_MODE is a real time input to select between Hi-Z and REF/N
divider mode while in test mode. Refer to Test Clarification Table.
27MHz Non-Spread Push-Pull output / True clock of low power LCDCLK output / True clock of
low power PCIEXCLK differential pair/ selected by SELPCIEX0_LCD# and SELLCD_27#. No
50ohm resistor to GND needed for differential outputs.
27MHz Spreading Push-Pull output / Complementary clock of LCDCLK_SS output /
Complementary clock of PCIEXCLK differential pair/ selected by SELPCIEX0_LCD# and
SELLCD_27#. No 50ohm resistor to GND needed for differential outputs.
True clock of 0.8V differential push-pull PCI_Express pair (no 50ohm resistor to GND needed)
Complement clock of 0.8V differential push-pull PCI_Express pair. (no 50ohm resistor to GND
needed)
Power supply for PCI Express clocks, nominal 3.3V
True clock of 0.8V differential push-pull PCI_Express pair (no 50ohm resistor to GND needed)
Complement clock of 0.8V differential push-pull PCI_Express pair. (no 50ohm resistor to GND
needed)
True clock of 0.8V differential push-pull PCI_Express pair (no 50ohm resistor to GND needed)
Complement clock of 0.8V differential push-pull PCI_Express pair. (no 50ohm resistor to GND
needed)
True clock of 0.8V push-pull differential SATA pair. (no 50ohm resistor to GND needed)
Complement clock of 0.8V push-pull differential SATA pair. (no 50ohm resistor to GND needed)
Power supply for PCI Express clocks, nominal 3.3V
Ground pin.
True clock of 0.8V differential push-pull PCI_Express pair (no 50ohm resistor to GND needed)
Complement clock of 0.8V differential push-pull PCI_Express pair. (no 50ohm resistor to GND
needed)
Real-time input pin that controls PCIEXCLK outputs that are selected through the I2c. 1 =
disabled, 0 = enabled.
9
10
11
12
13
14
15
16
*SELLCD_27#/PCICLK_F5
VttPWR_GD/PD#
VDD48
FSLA/USB_48MHz
GND
PCIeT_L9/DOTT_96MHzL
PCIeC_L9/DOTC_96MHzL
FSLB/TEST_MODE
I/O
IN
PWR
I/O
PWR
OUT
OUT
IN
17
27FIX/LCD_SSCGT/PCIeT_L0
OUT
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
27SS/LCD_SSCGC/PCIeC_L0
PCIeT_L1
PCIeC_L1
VDDPCIEX
PCIeT_L2
PCIeC_L2
PCIeT_L3
PCIeC_L3
SATACLKT_L
SATACLKC_L
VDDPCIEX
GND
PCIeT_L4
PCIeC_L4
*PEREQ3#
OUT
OUT
OUT
PWR
OUT
OUT
OUT
OUT
OUT
OUT
PWR
PWR
OUT
OUT
IN
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9LPR363
Datasheet
Pin Description (Continued)
PIN #
33
34
35
36
37
38
39
40
PIN NAME
PEREQ4#*
PWRSAVE#*
PCIeC_L5
PCIeT_L5
GND
PCIeC_L6
PCIeT_L6
PEREQ2#/PCIeC_L7
TYPE
IN
IN
OUT
OUT
PWR
OUT
OUT
I/O
DESCRIPTION
Real-time input pin that controls PCIEXCLK outputs that are selected through the I2c. 1 =
disabled, 0 = enabled.
Active-low input pin used to change frequency to underclocked entries in the ROM table that can
be pre-programmed through Byte 6 of the I2c.
Complement clock of 0.8V differential push-pull PCI_Express pair. (no 50ohm resistor to GND
needed)
True clock of 0.8V differential push-pull PCI_Express pair (no 50ohm resistor to GND needed)
Ground pin.
Complement clock of 0.8V differential push-pull PCI_Express pair. (no 50ohm resistor to GND
needed)
True clock of 0.8V differential push-pull PCI_Express pair (no 50ohm resistor to GND needed)
Real-time input pin that controls PCIEXCLK outputs that are selected through the I2c. 1 =
disabled, 0 = enabled. / Complement clock of differential low power PCI Express output. No
50ohm resistor to GND needed.
Real-time input pin that controls PCIEXCLK outputs that are selected through the I2c. 1 =
disabled, 0 = enabled. / True clock of differential low power PCI Express output. No 50ohm
resistor to GND needed.
Power supply for PCI Express clocks, nominal 3.3V
Complement clock of differential pair CPU output. / Complement clock of differential PCIEX pair.
These are 0.8V push pull outputs. No 50ohm resistor to GND needed.
True clock of differential pair CPU output. / True clock of differential PCIEX pair. These are 0.8V
push pull outputs. No 50ohm resistor to GND needed.
3.3V power for the PLL core.
Ground pin for the PLL core.
Voltage reference for low power outputs.
Complementary clock of differential pair of low power CPU outputs. Free running during iAMT.
No 50ohm resistor to GND needed.
True clock of differential pair of low power CPU outputs. Free running during iAMT. No 50ohm
resistor to GND needed.
Supply for CPU clocks, 3.3V nominal
Complementary clock of differential pair 0.8V push-pull CPU outputs. No 50ohm resistor to GND
needed.
True clock of differential pair 0.8V push-pull CPU outputs. No 50ohm resistor to GND needed.
Ground pin.
Clock pin of SMBus circuitry, 5V tolerant.
Data pin for SMBus circuitry, 5V tolerant.
Ref, XTAL power supply, nominal 3.3V
Crystal output, Nominally 14.318MHz
Crystal input, Nominally 14.318MHz.
Ground pin.
14.318 MHz reference clock.
14.318 MHz reference clock./ 3.3V tolerant input for CPU frequency selection. Refer to input
electrical characteristics for Vil_FS and Vih_FS values. /TEST_Sel: 3-level latched input to
enable test mode. Refer to Test Clarification Table
Stops all CPUCLK, except those set to be free running clocks
Stops all PCICLKs and PCIEXCLKs besides the free-running clocks at logic 0 level, when input
low
3.3V PCI clock output / Latch select input pin. 0 = PCIEXCLK, 1 = PEREQ#
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
PEREQ1#/PCIeT_L7
VDDPCIEX
CPUITPC_L2/PCIeC_L8
CPUITPT_L2/PCIeT_L8
VDDA
GNDA
VREF
CPUC_L1F
CPUT_L1F
VDDCPU
CPUC_L0
CPUT_L0
GND
SCLK
SDATA
VDDREF
X2
X1
GND
REF0
REF1/FSLC/TEST_SEL
CPU_STOP#
PCI/PCIEX_STOP#
PCICLK0/REQ_SEL**
I/O
PWR
OUT
OUT
PWR
PWR
PWR
OUT
OUT
PWR
OUT
OUT
PWR
IN
I/O
PWR
OUT
IN
PWR
OUT
I/O
IN
IN
I/O
1199—08/20/08
3
9LPR363
Datasheet
General Description
ICS9LPR363
is a low power CK505-compliant clock specification. This clock synthesizer provides a single chip solution for
next generation P4 Intel processors and Intel chipsets.
ICS9LPR363
is driven with a 14.318MHz crystal.
Block Diagram
USB_48MHz
Fixed PLL
X1
X2
Frequency
Dividers
PCIeT_L9/DOTT_96MHzL
PCIeC_L9/DOTC_96MHzL
XTAL
REF(1:0)
CPUCLKT (1:0)
CPUCLKC (1:0)
PLL
Array
Programmable
Frequency
Divider
Array
CPUCLKT2_ITP/PCIEXT8
CPUCLKC2_ITP/PCIEXC8
PCICLK_F(5:4)
STOP
Logic
PCICLK (3:0)
PCIEXT (7:1)
PCIEXC (7:1)
27FIX/LCD_SSCGT/PCIEX0T
27SS/LCD_SSCGT/PCIEX0C
SATACLKT
SATACLKC
SCLK
SDATA
FSLA
FSLB
FSLC
PEREQ#(4:1)
CPU_STOP#
PCI/PCIEX_STOP#
ITP_EN
REQ_SEL
TEST_SEL
TEST_MODE
SELPCIEX0_LCD#
SELLCD_27#
PWRSAVE#
Vtt_Pwr_GD/PD#
Control
Logic
Note: 1. VREF is not connected unless differential amplitude needs to be tuned
Power Supply
PIN NUMBER
VDD
Description
PCICLK outputs
48MHz,96Mhz, LCDCLK, Fix Digital,
Fix Analog
Master clock, CPU Analog
PCIEXT/C outputs
CPUT/C output
Xtal, REF
1,7
11
45
28, 42
50
56
GND
2,6
13
46
21, 29, 37
53
59
1199—08/20/08
4
9LPR363
Datasheet
Differential Amplitude control using VREF.
Rpull-up: Connected between Vref and Vdd=3.3V;
Rpull-down: Connected between Vref and GND
Keep Rpull-up=1K ohm and variable Rpull-down to measure CPU and PCIEX Vtop
Rpull-up (ohm) Rpull-down (ohm) CPU-T Vtop (mV) PCIEX-T Vtop (mV) SATA-T Vtop (mV)
1K
200
1155
1149
1136
1K
221
1092
1060
1063
1K
239
1054
1028
1040
1K
270
996
991
984
1K
301
943
946
931
1K
330
924
913
912
1K
360
898
888
885
1K
375
871
860
865
1K
390
867
837
822
1K
414
812
822
801
*Measurement based on Vtop-avg
**Test board trace impedance is 50ohms
Vdd=3.3V
Rpull-up=1K ohm
DUT
Vref
Rpull-down is variable
GND
1199—08/20/08
5
