Selectable between one SRC differential push-pull pair
and two single-ended outputs
Pin Configuration
PCI0/CR#_A
VDDPCI
PCI1/CR#_B
PCI2/TME
PCI3
PCI4/27_Select
PCI_F5/ITP_EN
GNDPCI
VDD48
USB_48MHz/FSLA
GND48
VDD96_IO
SRCT0/DOTT_96
SRCC0/DOTC_96
GND
VDDPLL3
27MHz_NonSS/SRCT1/SE1
27MHz_SS/SRCC1/SE2
GND
VDDPLL3_IO
SRCT2/SATAT
SRCC2/SATAC
GNDSRC
SRCT3/CR#_C
SRCC3/CR#_D
VDDSRC_IO
SRCT4
SRCC4
GNDSRC
SRCT9
SRCC9
SRCC11/CR#_G
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
SCLK
SDATA
REF0/FSLC/TEST_SEL
VDDREF
X1
X2
GNDREF
FSLB/TEST_MODE
CK_PWRGD/PD#
VDDCPU
CPUT0
CPUC0
GNDCPU
CPUT1_F
CPUC1_F
VDDCPU_IO
NC
CPUT2_ITP/SRCT8
CPUC2_ITP/SRCC8
VDDSRC_IO
SRCT7/CR#_F
SRCC7/CR#_E
GNDSRC
SRCT6
SRCC6
VDDSRC
PCI_STOP#
CPU_STOP#
VDDSRC_IO
SRCC10
SRCT10
SRCT11/CR#_H
64-TSSOP
* Internal Pull-Up Resistor
** Internal Pull-Down Resistor
64-TSSOP
27_Select (power on latch)
Pin13/14 & Pin17/18
0
DOT96, LCD_SS
Byte1 bit7 = 1.
1
SRC0, 27MHz Non SS & SS
Byte1 bit7 = 0.
Table 1: CPU Frequency Select Table
FS
L
C
B0b7
0
0
0
0
1
1
1
1
2
FS
L
B
B0b6
0
0
1
1
0
0
1
1
1
FS
L
A
B0b5
0
1
0
1
0
1
0
1
1
CPU
MHz
266.66
133.33
200.00
166.66
333.33
100.00
400.00
SRC
MHz
PCI
MHz
REF
MHz
U
SB
MHz
DOT
MHz
100.00
33.33
14.318
48.00
96.00
Reserved
1. FS
L
A and FS
L
B are low-threshold inputs.Please see V
IL_FS
and V
IH_FS
specifications in
the Input/Supply/Common Output Parameters Table for correct values.
Also refer to the Test Clarification Table.
2. FS
L
C is a three-level input. Please see the V
IL_FS
and V
IH_FS
specifications in the Input/Supply/Common Output Parameters Table for correct values.
1218—09/09/09
ADVANCE INFORMATION
documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals.
ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners.
9LPRS365
Integrated
Circuit
Systems, Inc.
ICS9LPRS365
Advance Information
TSSOP Pin Description
PIN #
PIN NAME
TYPE
DESCRIPTION
3.3V PCI clock output or Clock Request control A for either SRC0 or SRC2 pair
The power-up default is PCI0 output, but this pin may also be used as a Clock Request control of SRC pair
0 or SRC pair 2 via SMBus. Before configuring this pin as a Clock Request Pin, the PCI output must first
be disabled in byte 2, bit 0 of SMBus address space . After the PCI output is disabled (high-Z), the pin can
then be set to serve as a Clock Request pin for either SRC pair 2 or pair 0 using the CR#_A_EN bit
located in byte 5 of SMBUs address space.
Byte 5, bit 7
0 = PCI0 enabled (default)
1= CR#_A enabled. Byte 5, bit 6 controls whether CR#_A controls SRC0 or SRC2 pair
Byte 5, bit 6
0 = CR#_A controls SRC0 pair (default),
1= CR#_A controls SRC2 pair
Power supply pin for the PCI outputs, 3.3V nominal
3.3V PCI clock output/Clock Request control B for either SRC1 or SRC4 pair
The power-up default is PCI1 output, but this pin may also be used as a Clock Request control of SRC pair
1 or SRC pair 4 via SMBus. Before configuring this pin as a Clock Request Pin, the PCI output must first
be disabled in byte 2, bit 1 of SMBus address space . After the PCI output is disabled (high-Z), the pin can
then be set to serve as a Clock Request pin for either SRC pair 1 or pair 4 using the CR#_B_EN bit
located in byte 5 of SMBUs address space.
Byte 5, bit 5
0 = PCI1 enabled (default)
1= CR#_B enabled. Byte 5, bit 6 controls whether CR#_B controls SRC1 or SRC4 pair
Byte 5, bit 4
0 = CR#_B controls SRC1 pair (default)
1= CR#_B controls SRC4 pair
1
PCI0/CR#_A
I/O
2
VDDPCI
PWR
3
PCI1/CR#_B
I/O
4
PCI2/TME
I/O
3.3V PCI clock output / Trusted Mode Enable (TME) Latched Input. This pin is sampled on power-up as
follows
0 = Overclocking of CPU and SRC Allowed
1 = Overclocking of CPU and SRC NOT allowed
After being sampled on power-up, this pin becomes a 3.3V PCI Output
3.3V PCI clock output.
3.3V PCI clock output / 27MH mode select for pin17, 18 strap. On powerup, the logic value on this pin
determines the power-up default of DOT_96/SRC0 and 27MHz/SRC1 output and the function table for the
pin17 and pin18.
Free running PCI clock output and ITP/SRC8 enable strap. This output is not affected by the state of the
PCI_STOP# pin. On powerup, the state of this pin determines whether pins 46 and 47 are an ITP or SRC
pair.
0 =SRC8/SRC8#
1 = ITP/ITP#
Ground for PCI clocks.
Power supply for USB clock, nominal 3.3V.
Fixed 48MHz USB clock output. 3.3V./ 3.3V tolerant input for CPU frequency selection. Refer to input
electrical characteristics for Vil_FS and Vih_FS values.
Ground pin for the 48MHz outputs.
1.05V to 3.3V from external power supply
True clock of SRC or DOT96. The power-up default function depends on 27_Select, 1= SRC0,
0=DOT96
Complement clock of SRC or DOT96. The power-up default function depends on 27_Select, 1= SRC0,
0=DOT96
Ground pin for the DOT96 clocks.
Power supply for SRC / SE1 and SE2 clocks, 3.3V nominal.
5
6
PCI3
PCI4/27_Select
OUT
I/O
7
PCI_F5/ITP_EN
I/O
8
9
10
11
12
13
14
15
16
GNDPCI
VDD48
USB_48MHz/FSLA
GND48
VDD96_IO
DOTT_96/SRCT0
DOTC_96/SRCC0
GND
VDD
PWR
PWR
I/O
PWR
PWR
OUT
OUT
PWR
PWR
1218—09/09/09
2
Integrated
Circuit
Systems, Inc.
ICS9LPRS365
Advance Information
TSSOP Pin Description (Continued)
PIN #
17
PIN NAME
27MHz_NonSS/SRCT1/SE1
TYPE
OUT
DESCRIPTION
True clock of differential SRC1 clock pair / 3.3V single-ended output. 27_Select determines the power-up
default, 1=27MHz non-spread SE clock, 0 = LCD_SST 100MHz differential clock. See table 2 for more
information.
Complement clock of differential SRC1 clock pair / 3.3V single-ended output. 27_Select determines the
power-up default, 1=27MHz spread SE clock, 0 = LCD_SSC 100MHz differential clock. See table 2 for
more information.
Ground pin for SRC / SE1 and SE2 clocks, PLL3.
1.05V to 3.3V from external power supply
True clock of differential SRC/SATA clock pair.
Complement clock of differential SRC/SATA clock pair.
Ground pin for SRC clocks.
True clock of differential SRC clock pair/ Clock Request control C for either SRC0 or SRC2 pair
The power-up default is SRCCLK3 output, but this pin may also be used as a Clock Request control of
SRC pair 0 or SRC pair 2 via SMBus. Before configuring this pin as a Clock Request Pin, the SRC3 output
must first be disabled in byte 4, bit 7 of SMBus address space . After the SRC3 output is disabled, the pin
can then be set to serve as a Clock Request pin for either SRC pair 2 or pair 0 using the CR#_C_EN bit
located in byte 5 of SMBUs address space.
Byte 5, bit 3
0 = SRC3 enabled (default)
1= CR#_C enabled. Byte 5, bit 2 controls whether CR#_C controls SRC0 or SRC2 pair
Byte 5, bit 2
0 = CR#_C controls SRC0 pair (default),
1= CR#_C controls SRC2 pair
Complementary clock of differential SRC clock pair/ Clock Request control D for either SRC1 or SRC4
pair
The power-up default is SRCCLK3 output, but this pin may also be used as a Clock Request control of
SRC pair 1 or SRC pair 4 via SMBus. Before configuring this pin as a Clock Request Pin, the SRC3 output
must first be disabled in byte 4, bit 7 of SMBus address space . After the SRC3 output is disabled, the pin
can then be set to serve as a Clock Request pin for either SRC pair 1 or pair 4 using the CR#_D_EN bit
located in byte 5 of SMBUs address space.
Byte 5, bit 1
0 = SRC3 enabled (default)
1= CR#_D enabled. Byte 5, bit 0 controls whether CR#_D controls SRC1 or SRC4 pair
Byte 5, bit 0
0 = CR#_D controls SRC1 pair (default),
1= CR#_D controls SRC4 pair
1.05V to 3.3V from external power supply
True clock of differential SRC clock pair 4
Complement clock of differential SRC clock pair 4
Ground pin for SRC clocks.
True clock of differential SRC clock pair.
Complement clock of differential SRC clock pair.
SRC11 complement /Clock Request control for SRC9 pair
The power-up default is SRC11#, but this pin may also be used as a Clock Request control of SRC9 via
SMBus. Before configuring this pin as a Clock Request Pin, the SRC11 output pair must first be disabled in
byte 3, bit 7 of SMBus configuration space After the SRC11 output is disabled (high-Z), the pin can then be
set to serve as a Clock Request for SRC9 pair using byte 6, bit 5 of SMBus configuration space
Byte 6, bit 5
0 = SRC11# enabled (default)
1= CR#_G controls SRC9
18
19
20
21
22
23
27MHz_SS/SRCC1/SE2
GND
VDDPLL3_IO
SRCT2/SATAT
SRCC2/SATAC
GNDSRC
OUT
PWR
PWR
OUT
OUT
PWR
24
SRCT3/CR#_C
I/O
25
SRCC3/CR#_D
I/O
26
27
28
29
30
31
VDDSRC_IO
SRCT4
SRCC4
GNDSRC
SRCT9
SRCC9
PWR
I/O
I/O
PWR
OUT
OUT
32
SRCC11/CR#_G
I/O
1218—09/09/09
3
Integrated
Circuit
Systems, Inc.
ICS9LPRS365
Advance Information
TSSOP Pin Description (Continued)
PIN #
PIN NAME
TYPE
DESCRIPTION
SRC11 true or Clock Request control H for SRC10 pair
The power-up default is SRC11, but this pin may also be used as a Clock Request control of SRC10 via
SMBus. Before configuring this pin as a Clock Request Pin, the SRC11 output pair must first be disabled in
byte 3, bit 7 of SMBus configuration space After the SRC11 output is disabled (high-Z), the pin can then be
set to serve as a Clock Request for SRC10 pair using byte 6, bit 4 of SMBus configuration space
Byte 6, bit 4
0 = SRC11 enabled (default)
1= CR#_H controls SRC10.
True clock of differential SRC clock pair.
Complement clock of differential SRC clock pair.
1.05V to 3.3V from external power supply
Stops all CPU Clocks, except those set to be free running clocks. In AMT mode 3 bits are shifted in from
the ICH to set the FSC, FSB, FSA values
Stops all PCI Clocks, except those set to be free running clocks. In AMT mode 3 bits are shifted in from
the ICH to set the FSC, FSB, FSA values
VDD pin for SRC Pre-drivers, 3.3V nominal
Complement clock of low power differential SRC clock pair.
True clock of low power differential SRC clock pair.
Ground for SRC clocks
SRC7 complement or Clock Request control E for SRC6 pair
The power-up default is SRC7#, but this pin may also be used as a Clock Request control of SRC6 via
SMBus. Before configuring this pin as a Clock Request Pin, the SRC7 output pair must first be disabled in
byte 3, bit 3 of SMBus configuration space . After the SRC output is disabled (high-Z), the pin can then be
set to serve as a Clock Request for SRC6 pair using byte 6, bit 7 of SMBus configuration space
Byte 6, bit 7
0 = SRC7# enabled (default)
1= CR#_E controls SRC6.
SRC7 true or Clock Request control 8 for SRC8 pair
The power-up default is SRC7, but this pin may also be used as a Clock Request control of SRC8 via
SMBus. Before configuring this pin as a Clock Request Pin, the SRC7 output pair must first be disabled in
byte 3, bit 3 of SMBus configuration space After the SRC output is disabled (high-Z), the pin can then be
set to serve as a Clock Request for SRC8 pair using byte 6, bit 6 of SMBus configuration space
Byte 6, bit 6
0 = SRC7# enabled (default)
1 = CR#_F controls SRC8.
1.05V to 3.3V from external power supply
Complement clock of low power differential CPU2/Complement clock of differential SRC pair. The function
of this pin is determined by the latched input value on pin 7, PCIF5/ITP_EN on powerup. The function is as
follows:
Pin 7 latched input Value
0 = SRC8#
1 = ITP#
True clock of low power differential CPU2/True clock of differential SRC pair. The function of this pin is
determined by the latched input value on pin 7, PCIF5/ITP_EN on powerup. The function is as follows:
Pin 7 latched input Value
0 = SRC8
1 = ITP
No Connect
33
SRCT11/CR#_H
I/O
34
35
36
37
38
39
40
41
42
SRCT10
SRCC10
VDDSRC_IO
CPU_STOP#
PCI_STOP#
VDDSRC
SRCC6
SRCT6
GNDSRC
OUT
OUT
PWR
IN
IN
PWR
OUT
OUT
PWR
43
SRCC7/CR#_E
I/O
44
SRCT7/CR#_F
I/O
45
VDDSRC_IO
PWR
46
CPUC2_ITP/SRCC8
OUT
47
CPUT2_ITP/SRCT8
OUT
48
NC
N/A
1218—09/09/09
4
Integrated
Circuit
Systems, Inc.
ICS9LPRS365
Advance Information
TSSOP Pin Description (Continued)
PIN #
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
PIN NAME
VDDCPU_IO
CPUC1_F
CPUT1_F
GNDCPU
CPUC0
CPUT0
VDDCPU
CK_PWRGD/PD#
FSLB/TEST_MODE
GNDREF
X2
X1
VDDREF
REF0/FSLC/TEST_SEL
SDATA
SCLK
TYPE
PWR
OUT
OUT
PWR
OUT
OUT
PWR
IN
IN
PWR
OUT
IN
PWR
I/O
I/O
IN
1.05V to 3.3V from external power supply
Complement clock of low power differenatial CPU clock pair. This clock will be free-running during iAMT.
True clock of low power differential CPU clock pair. This clock will be free-running during iAMT.
Ground Pin for CPU Outputs
Complement clock of low power differential CPU clock pair.
True clock of low power differential CPU clock pair.
Power Supply 3.3V nominal.
Notifies CK505 to sample latched inputs, or iAMT entry/exit, or PWRDWN# mode
3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and
Vih_FS values. TEST_MODE is a real time input to select between Hi-Z and REF/N divider mode while in
test mode. Refer to Test Clarification Table.
Ground pin for crystal oscillator circuit
Crystal output, nominally 14.318MHz.
Crystal input, Nominally 14.318MHz.
Power pin for the REF outputs, 3.3V nominal.
3.3V 14.318MHz reference clock/3.3V tolerant low threshold input for CPU frequency selection. Refer to
input electrical characteristics for Vil_FS and Vih_FS values/ TEST_SEL: 3-level latched input to enable
