DATASHEET
Advance Information
Programmable System Clock Chip for ATI RS790 - K8
TM
based
Systems
Recommended Application:
ATI RS790 systems using AMD K8 processors
Output Features:
•
2 - Greyhound compatible K8 CPU pair
•
6 - low-power differential SRC pairs
•
2 - low-power differential SouthBridge SRC pairs
•
4 - low-power differential ATIG pairs
•
1 - Selectable low-power differential 100MHz non-
spread SATA/ SRC output
•
1 - Selectable 100MHz low-power differential/ 66 MHz
single-ended HTT clock
•
2 - 48MHz USB clock
•
3 - 14.318MHz Reference clock
9LPRS471C
Key Specifications:
•
CPU outputs cycle-to-cycle jitter < 85ps
•
SRC outputs cycle-to-cycle jitter < 125ps
•
ATIG outputs cycle-to-cycle jitter < 125ps
•
+/- 300ppm frequency accuracy on CPU, SRC & ATIG
clocks
Features/Benefits:
•
CPU, ATIG, SB_SRC and SRC outputs are
independently programmable for frequency
•
Spread Spectrum for EMI reduction
•
Outputs may be disabled via SMBus
•
External crystal load capacitors for maximum
frequency accuracy
•
Meets PCIEX Gen2 specifications
HTT0C_LPRS/66M
HTT0T_LPRS/66M
REF0/SEL_HTT66
REF1/SEL_SATA
64
48MHz_1 1
48MHz_0 2
GND48 3
SMBCLK 4
SMBDAT 5
SRC5C_LPRS 6
SRC5T_LPRS 7
SRC4C_LPRS 8
SRC4T_LPRS 9
GNDSRC 10
VDDSRC 11
SRC3C_LPRS 12
SRC3T_LPRS 13
SRC2C_LPRS 14
SRC2T_LPRS 15
VDDSRC 16
17
GNDSRC
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48 VDDCPU
47 GNDCPU
46 CPUKG1T_LPRS
45 CPUKG1C_LPRS
44 VDDA
43 GNDA
42 GNDSATA
41 SRC6T/SATAT_LPRS
40 SRC6C/SATAC_LPRS
39 VDDSATA
38 ATIG0T_LPRS
37 ATIG0C_LPRS
36 ATIG1T_LPRS
35 ATIG1C_LPRS
34 VDDATIG
33 GNDATIG
9LPRS471C
18
SRC1C_LPRS
19
SRC1T_LPRS
20
SRC0C_LPRS
21
SRC0T_LPRS
22
SB_SRC1C_LPRS
23
SB_SRC1T_LPRS
24
GNDSB_SRC
25
VDDSB_SRC
26
SB_SRC0C_LPRS
27
SB_SRC0T_LPRS
28
GNDATIG
29
ATIG3C_LPRS
30
ATIG3T_LPRS
31
ATIG2C_LPRS
32
ATIG2T_LPRS
64-Pin MLF
* Internal Pull-Up Resistor
** Internal Pull-Down Resistor
IDT
®
Programmable System Clock Chip for ATI RS790 - K8
TM
based Systems
CPUKG0C_LPRS
CPUKG0T_LPRS
Pin Configuration
GNDREF
VDDREF
RESTORE#
GNDHTT
VDDHTT
VDD48
REF2
PD#
X2
X1
1398—05/23/12
1
9LPRS471C
Frequency Timing Generator for Peripherals
Advance Information
Pin Description
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
PIN NAME
TYPE
DESCRIPTION
48MHz_1
48MHz_0
GND48
SMBCLK
SMBDAT
SRC5C_LPRS
SRC5T_LPRS
SRC4C_LPRS
SRC4T_LPRS
GNDSRC
VDDSRC
SRC3C_LPRS
SRC3T_LPRS
SRC2C_LPRS
SRC2T_LPRS
VDDSRC
GNDSRC
SRC1C_LPRS
SRC1T_LPRS
SRC0C_LPRS
SRC0T_LPRS
SB_SRC1C_LPRS
SB_SRC1T_LPRS
GNDSB_SRC
VDDSB_SRC
SB_SRC0C_LPRS
SB_SRC0T_LPRS
GNDATIG
ATIG3C_LPRS
ATIG3T_LPRS
ATIG2C_LPRS
ATIG2T_LPRS
GNDATIG
VDDATIG
ATIG1C_LPRS
ATIG1T_LPRS
OUT
OUT
GND
IN
I/O
OUT
OUT
OUT
OUT
GND
PWR
OUT
OUT
OUT
OUT
PWR
GND
OUT
OUT
OUT
OUT
OUT
OUT
GND
PWR
OUT
OUT
GND
OUT
OUT
OUT
OUT
GND
PWR
OUT
OUT
48MHz clock output.
48MHz clock output.
Ground pin for the 48MHz outputs
Clock pin of SMBus circuitry, 5V tolerant.
Data pin for SMBus circuitry, 5V tolerant.
Complement clock of low power differential SouthBridge SRC clock pair. (no 50ohm shunt resistor to GND
and no 33 ohm series resistor needed
True clock of low power differential SRC clock pair. (no 50ohm shunt resistor to GND and no 33 ohm
series resistor needed
Complement clock of low power differential SouthBridge SRC clock pair. (no 50ohm shunt resistor to GND
and no 33 ohm series resistor needed
True clock of low power differential SRC clock pair. (no 50ohm shunt resistor to GND and no 33 ohm
series resistor needed
Ground pin for the SRC outputs
Supply for SRC core, 3.3V nominal
Complement clock of low power differential SouthBridge SRC clock pair. (no 50ohm shunt resistor to GND
and no 33 ohm series resistor needed
True clock of low power differential SRC clock pair. (no 50ohm shunt resistor to GND and no 33 ohm
series resistor needed
Complement clock of low power differential SouthBridge SRC clock pair. (no 50ohm shunt resistor to GND
and no 33 ohm series resistor needed
True clock of low power differential SRC clock pair. (no 50ohm shunt resistor to GND and no 33 ohm
series resistor needed
Supply for SRC core, 3.3V nominal
Ground pin for the SRC outputs
Complement clock of low power differential SouthBridge SRC clock pair. (no 50ohm shunt resistor to GND
and no 33 ohm series resistor needed
True clock of low power differential SRC clock pair. (no 50ohm shunt resistor to GND and no 33 ohm
series resistor needed
Complement clock of low power differential SouthBridge SRC clock pair. (no 50ohm shunt resistor to GND
and no 33 ohm series resistor needed
True clock of low power differential SRC clock pair. (no 50ohm shunt resistor to GND and no 33 ohm
series resistor needed
Complement clock of low power differential SouthBridge SRC clock pair. (no 50ohm shunt resistor to GND
and no 33 ohm series resistor needed
True clock of low power differential SouthBridge SRC clock pair. (no 50ohm shunt resistor to GND and no
33 ohm series resistor needed
Ground pin for the SB_SRC outputs
Supply for SRC core, 3.3V nominal
Complement clock of low power differential SouthBridge SRC clock pair. (no 50ohm shunt resistor to GND
and no 33 ohm series resistor needed
True clock of low power differential SouthBridge SRC clock pair. (no 50ohm shunt resistor to GND and no
33 ohm series resistor needed
Ground pin for the ATIG outputs
Complementary clock of low-power differential push-pull PCI-Express pair with integrated series resistor.
(no 50ohm shunt resistor to GND and no 33 ohm series resistor needed)
True clock of low-power differential push-pull PCI-Express pair with integrated series resistor. (no 50ohm
shunt resistor to GND and no 33 ohm series resistor needed)
Complementary clock of low-power differential push-pull PCI-Express pair with integrated series resistor.
(no 50ohm shunt resistor to GND and no 33 ohm series resistor needed)
True clock of low-power differential push-pull PCI-Express pair with integrated series resistor. (no 50ohm
shunt resistor to GND and no 33 ohm series resistor needed)
Ground pin for the ATIG outputs
Power supply for ATIG core, nominal 3.3V
Complementary clock of low-power differential push-pull PCI-Express pair with integrated series resistor.
(no 50ohm shunt resistor to GND and no 33 ohm series resistor needed)
True clock of low-power differential push-pull PCI-Express pair with integrated series resistor. (no 50ohm
shunt resistor to GND and no 33 ohm series resistor needed)
IDT
®
Programmable System Clock Chip for ATI RS790 - K8
TM
based Systems
1398—05/23/12
2
9LPRS471C
Frequency Timing Generator for Peripherals
Advance Information
Pin Description (Continued)
PIN #
38
39
40
41
42
43
44
45
46
47
48
49
50
51
PIN NAME
TYPE
DESCRIPTION
ATIG0T_LPRS
VDDSATA
SRC6C/SATAC_LPRS
SRC6T/SATAT_LPRS
GNDSATA
GNDA
VDDA
CPUKG1C_LPRS
CPUKG1T_LPRS
GNDCPU
VDDCPU
CPUKG0C_LPRS
CPUKG0T_LPRS
PD#
OUT
PWR
OUT
OUT
GND
GND
PWR
OUT
OUT
GND
PWR
OUT
OUT
IN
True clock of low-power differential push-pull PCI-Express pair with integrated series resistor. (no 50ohm
shunt resistor to GND and no 33 ohm series resistor needed)
Power supply for SATA core logic, nominal 3.3V
Complement clock of low power differential SRC/SATA clock pair. (no 50ohm shunt resistor to GND and
no 33 ohm series resistor needed
True clock of low power differential SRC clock pair. (no 50ohm shunt resistor to GND and no 33 ohm
series resistor needed
Ground pin for the SRC outputs
Ground for the Analog Core
3.3V Power for the Analog Core
Complementary signal of low-power differential push-pull AMD K8 "Greyhound" clock with integrated
series resistor.(no 33 ohm series resistor needed)
True signal of low-power differential push-pull AMD K8 "Greyhound" clock with integrated series resistor.
(no 33 ohm series resistor needed)
Ground pin for the CPU outputs
Supply for CPU core, 3.3V nominal
Complementary signal of low-power differential push-pull AMD K8 "Greyhound" clock with integrated series
resistor. (no 33 ohm series resistor needed)
True signal of low-power differential push-pull AMD K8 "Greyhound" clock with integrated series
resistor.(no 33 ohm series resistor needed)
Enter /Exit Power Down.
0 = Power Down, 1 = normal operation.
Open Drain I/O. As an input it restores the PLL's to power up default state. As an output, this signal is driven low
when the internal watchdog hardware timer expires. It is cleared when the internal watchdog hardware timer is
reset or disabled. The input is falling edge triggered.
0 = Restore Settings, 1 = normal operation.
52
53
54
RESTORE#
GNDHTT
HTT0C_LPRS/66M
I/O
PWR
OUT
55
56
57
58
59
60
61
62
63
64
HTT0T_LPRS/66M
VDDHTT
REF2
REF1/SEL_SATA
REF0/SEL_HTT66
VDDREF
GNDREF
X1
X2
VDD48
OUT
PWR
OUT
I/O
I/O
PWR
GND
IN
OUT
PWR
Ground pin for the HTT outputs
Complementary signal of low-power differential push-pull hypertransport clock with integrated series
resistor. (no 50ohm shunt resistor to GND and no 33 ohm series resistor needed) / 3.3V single ended
66MHz hyper transport clock
True signal of low-power differential push-pull hypertransport clock with integrated series resistor. (no
50ohm shunt resistor to GND and no 33 ohm series resistor needed) / 3.3V single ended 66MHz hyper
transport clock
Supply for HTT clocks, nominal 3.3V.
14.318 MHz reference clock, 3.3V
14.318 MHz 3.3V reference clock./ 3.3V tolerant latched input to select function of SRC6/SATA output
0 = 100MHz differential spreading SRC clock, 1 = 100MHz non-spreading differential SATA clock
14.318 MHz 3.3V reference clock./ 3.3V tolerant latched input to select Hyper Transport Clock Frequency.
0 = 100MHz differential HTT clock, 1 = 66MHz 3.3V single ended HTT clock
Ref, XTAL power supply, nominal 3.3V
Ground pin for the REF outputs.
Crystal input, nominally 14.318MHz
Crystal output, nominally 14.318MHz
Power pin for the 48MHz outputs and core. 3.3V
IDT
®
Programmable System Clock Chip for ATI RS790 - K8
TM
based Systems
1398—05/23/12
3
9LPRS471C
Frequency Timing Generator for Peripherals
Advance Information
General Description
The
9LPRS471C
is a main clock synthesizer chip that provides all clocks required for ATI RS7xx-based
systems.using AMD processors. An SMBus interface allows full control of the device.
Block Diagram
X1
X2
14.318MHz
REF
OSC
48MHz_(1:0)
Fixed PLL4
EXACT 48MHz
SEL_SATA
100MHz
SRC6/SATA
SS
PLL
SB_SRC
(-0.5% DWN SP)
800MHz
SS
PLL
SB_SRC/SRC
100MHz
SB_SRC(1:0)
SRC ZDB PLL
400 to 900 MHz
PWD @
600MHz/6
SRC(5:0)
SEL_HTT66
HTT_100T/66
HTT_100C/66
CPUKG(1:0)
HTT 100MHz
SS PLL
HTT 66MHz
200MHz
ATIG ZDB PLL
ATIG(3:0)
PD#
SEL_HTT66
SEL_SATA
SMBCLK
SMBDAT
RESTORE#
CLKREQ(A:B)#
MODE
Control
Logic
9LPR471C Power Group Table
Pin Number
Description
VDD
GND
64
3
48M I/O & Core
11, 16
10, 17
SRC & SRCI/O I/O & Core; SRC PLL Analog
25
24
SB_SRCI/O I/O & Core; SB_SRC PLL Analog / Digital
34
28, 33
ATIG I/O & Core; ATIG PLL Analog
39
42
SATA I/O & Core; FIX PLL Analog / Digital
44
43
ATIG PLL & SRC PLL Digital
48
47
CPU I/O & Core; CPU PLL Analog / Digital
56
53
HTT I/O & Core
60
61
Crystal, REF I/O & Core
IDT
®
Programmable System Clock Chip for ATI RS790 - K8
TM
based Systems
1398—05/23/12
4
9LPRS471C
Frequency Timing Generator for Peripherals
Advance Information
Table1: CPU and HTT Frequency Selection Table
Byte 3
HTT
HTT
Single-ended Differential
Bit4
Bit3
Bit2
Bit1
Bit0
CPU
(MHz)
CPU
CPU
CPU
CPU
CPU
SEL_HTT66 = 1 SEL_HTT66 = 0
FS4
FS3
FS2
FS1
FS0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
200.00
205.00
210.00
215.00
220.00
225.00
230.00
235.00
240.00
245.00
250.00
255.00
260.00
265.00
270.00
200.00
280.00
285.00
290.00
295.00
300.00
305.00
310.00
315.00
320.00
325.00
330.00
335.00
340.00
345.00
350.00
355.00
66.67
68.33
70.00
71.67
73.33
75.00
76.67
78.33
80.00
81.67
83.33
85.00
86.67
88.33
90.00
66.67
93.33
95.00
96.67
98.33
100.00
101.67
103.33
105.00
106.67
108.33
110.00
111.67
113.33
115.00
116.67
118.33
100.00
102.50
105.00
107.50
110.00
112.50
115.00
117.50
120.00
122.50
125.00
127.50
130.00
132.50
135.00
100.00
140.00
142.50
145.00
147.50
150.00
152.50
155.00
157.50
160.00
162.50
165.00
167.50
170.00
172.50
175.00
177.50
Spread
%
CPU
(B6b6=1
OverClock %
and
B3b5=1)
0%
2%
5%
8%
10%
13%
15%
18%
20%
23%
25%
28%
30%
33%
35%
0%
40%
43%
45%
48%
50%
53%
55%
58%
60%
63%
65%
68%
70%
73%
75%
78%
IDT
®
Programmable System Clock Chip for ATI RS790 - K8
TM
based Systems
Depends on SB_SRC PLL. See Table 4.
1398—05/23/12
5
