DATASHEET
PROGRAMMABLE SYSTEM CLOCK CHIP FOR ATI RD790-K8
TM
BASED SYSTEMS
9LPRS477D
General Description
The 9LPRS477D is a main clock synthesizer chip that
provides all clocks required for ATI RD7xx-based systems
using AMD processors. An SMBus interface allows full
control of the device.
Features/Benefits
•
CPU, ATIG, SB_SRC and SRC outputs are
•
•
•
•
•
independently programmable for frequency
Spread Spectrum for EMI reduction
Outputs may be disabled via SMBus
External crystal load capacitors for maximum frequency
accuracy
Meets PCIEX Gen2 specifications
Meets 30kHz to 33kHz SRC modulation rate specification
for USB3.0
CPU outputs cycle-to-cycle jitter < 85ps
SRC outputs cycle-to-cycle jitter < 125ps
ATIG outputs cycle-to-cycle jitter < 125ps
± 300ppm frequency accuracy on CPU, SRC & ATIG
clocks
Recommended Application
ATI RS780/RS790/RD790/RS880 systems using AMD K8
processors
Output Features
•
•
•
•
•
•
•
•
2 - Greyhound compatible K8 CPU pairs
6 - low-power differential SRC pairs
2 - low-power differential SouthBridge SRC pairs
4 - low-power differential ATIG pairs
1 - Selectable low-power differential 100MHz non-spread
SATA/ SRC output
1 - Selectable 100MHz low-power differential/ 66 MHz
single-ended HTT clock
2 - 48MHz USB clocks
3 - 14.318MHz Reference clocks
Key Specifications
•
•
•
•
Pin Configuration
REF2/SEL_OC_MODE**
HTT0C_LPRS/66M
HTT0T_LPRS/66M
REF0/SEL_HTT66
CPUKG0C_LPRS
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
ATIG3C_LPRS
ATIG2C_LPRS
ATIG3T_LPRS
ATIG2T_LPRS
CPUKG0T_LPRS
REF1/SEL_SATA
RESTORE#
GNDREF
VDDREF
GNDHTT
VDDHTT
VDD48
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
**SEL_DOC/48MHz_1
**SEL_CPU1#/48MHz_0
GND48
SMBCLK
SMBDAT
**DOC_0/SRC5C_LPRS
**DOC_1/SRC5T_LPRS
SRC4C_LPRS
SRC4T_LPRS
GNDSRC
VDDSRC
SRC3C_LPRS
SRC3T_LPRS
SRC2C_LPRS
SRC2T_LPRS
VDDSRC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SRC1C_LPRS
SRC1T_LPRS
SRC0C_LPRS
GNDSRC
VDDCPU
GNDCPU
CPUKG1T_LPRS/SRC7T_LPRS
CPUKG1C_LPRS/SRC7C_LPRS
VDDA
GNDA
GNDSATA
SRC6T/SATAT_LPRS
SRC6C/SATAC_LPRS
VDDSATA
ATIG0T_LPRS
ATIG0C_LPRS
ATIG1T_LPRS
ATIG1C_LPRS
VDDATIG
GNDATIG
ICS9LPRS477D
SB_SRC1C_LPRS
SB_SRC1T_LPRS
SB_SRC0C_LPRS
SB_SRC0T_LPRS
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
SRC0T_LPRS
GNDSB_SRC
VDDSB_SRC
GNDATIG
64-Pin MLF
* Internal Pull-Up Resistor
** Internal Pull-Down Resistor
IDT®
PROGRAMMABLE SYSTEM CLOCK CHIP FOR ATI RD790-K8
TM
BASED SYSTEMS
PD#
X1
X2
1
9LPRS477D
REV C 010715
9LPRS477D
PROGRAMMABLE SYSTEM CLOCK CHIP FOR ATI RD790-K8
TM
BASED SYSTEMS
Pin Descriptions
PIN #
1
PIN NAME
**SEL_DOC/48MHz _1
PIN TYPE
I/O
DESCRIPTION
SEl_DOC: latched input to s elect pin functionality
1 = DOC input.
0 = SRCCLK5
/ 48MHz cloc k output.
SEL_CPU1 latched input to select pin functionality
1 = SRCCLK7
0 = CPUKG1
/ 48MHz cloc k output.
Ground pin for the 48MHz outputs
Clock pin of SMBus circuitry, 5V tolerant.
Data pin for SMBus circuitry, 5V tolerant.
Dynamic Over Clocking pin: real time frequency selection 0: Normal; 1: Frequency will transition to a
preprogrammed value in the I2c.
/ Complement clock of low power differential SRC clock pair. (no 50ohm shunt resistor to GND and no 33 ohm
s eries resistor needed
Dynamic Over Clocking pin: real time frequency selection 0: Normal; 1: Frequency will transition to a
preprogrammed value in the I2c.
/ True clock of low power differential SRC clock pair. (no 50ohm shunt resistor to GND and no 33 ohm series
resistor needed
Complement clock of low power differential SouthBridge SRC clock pair. (no 50ohm shunt resistor to GND and no
33 ohm series resistor needed
True clock of low power differential SRC clock pair. (no 50ohm s hunt res istor to GND and no 33 ohm s eries
resistor needed
Ground pin for the SRC outputs
Supply for SRC core, 3.3V nominal
Complement clock of low power differential SouthBridge SRC clock pair. (no 50ohm shunt resistor to GND and no
33 ohm series resistor needed
True clock of low power differential SRC clock pair. (no 50ohm s hunt res istor to GND and no 33 ohm s eries
resistor needed
Complement clock of low power differential SouthBridge SRC clock pair. (no 50ohm shunt resistor to GND and no
33 ohm series resistor needed
True clock of low power differential SRC clock pair. (no 50ohm s hunt res istor to GND and no 33 ohm s eries
resistor needed
Supply for SRC core, 3.3V nominal
Ground pin for the SRC outputs
Complement clock of low power differential SouthBridge SRC clock pair. (no 50ohm shunt resistor to GND and no
33 ohm series resistor needed
True clock of low power differential SRC clock pair. (no 50ohm s hunt res istor to GND and no 33 ohm s eries
resistor needed
Complement clock of low power differential SouthBridge SRC clock pair. (no 50ohm shunt resistor to GND and no
33 ohm series resistor needed
True clock of low power differential SRC clock pair. (no 50ohm s hunt res istor to GND and no 33 ohm s eries
resistor needed
Complement clock of low power differential SouthBridge SRC clock pair. (no 50ohm shunt resistor to GND and no
33 ohm series resistor needed
True clock of low power differential SouthBridge SRC clock pair. (no 50ohm shunt resistor to GND and no 33 ohm
s eries resistor needed
Ground pin for the SB_SRC outputs
Supply for SRC core, 3.3V nominal
Complement clock of low power differential SouthBridge SRC clock pair. (no 50ohm shunt resistor to GND and no
33 ohm series resistor needed
True clock of low power differential SouthBridge SRC clock pair. (no 50ohm shunt resistor to GND and no 33 ohm
s eries resistor needed
Ground pin for the ATIG outputs
Complementary clock of low-power differential push-pull PCI-Express pair with integrated series resistor. (no
50ohm shunt res istor to GND and no 33 ohm s eries resistor needed)
True clock of low-power differential push-pull PCI-Express pair with integrated series resistor. (no 50ohm shunt
resistor to GND and no 33 ohm series resistor needed)
Complementary clock of low-power differential push-pull PCI-Express pair with integrated series resistor. (no
50ohm shunt res istor to GND and no 33 ohm s eries resistor needed)
True clock of low-power differential push-pull PCI-Express pair with integrated series resistor. (no 50ohm shunt
resistor to GND and no 33 ohm series resistor needed)
2
3
4
5
6
**SEL_CPU1#/48MHz_0
GND48
SMBCLK
SMBDAT
**DOC_0/SRC5C_LPRS
I/O
GND
IN
I/O
OUT
7
**DOC_1/SRC5T_LPRS
OUT
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
SRC4C_LPRS
SRC4T_LPRS
GNDSRC
VDDSRC
SRC3C_LPRS
SRC3T_LPRS
SRC2C_LPRS
SRC2T_LPRS
VDDSRC
GNDSRC
SRC1C_LPRS
SRC1T_LPRS
SRC0C_LPRS
SRC0T_LPRS
SB_SRC1C_LPRS
SB_SRC1T_LPRS
GNDSB_SRC
VDDSB_SRC
SB_SRC0C_LPRS
SB_SRC0T_LPRS
GNDATIG
ATIG3C_LPRS
ATIG3T_LPRS
ATIG2C_LPRS
ATIG2T_LPRS
OUT
OUT
GND
PWR
OUT
OUT
OUT
OUT
PWR
GND
OUT
OUT
OUT
OUT
OUT
OUT
GND
PWR
OUT
OUT
GND
OUT
OUT
OUT
OUT
IDT®
PROGRAMMABLE SYSTEM CLOCK CHIP FOR ATI RD790-K8
TM
BASED SYSTEMS
2
9LPRS477D
REV C 010715
9LPRS477D
PROGRAMMABLE SYSTEM CLOCK CHIP FOR ATI RD790-K8
TM
BASED SYSTEMS
Pin Descriptions (cont.)
PIN #
33 GNDATIG
34 VDDATIG
35
36
37
38
39
40
41
42
43
44
45
PIN NAME
PIN TYPE
DESCRIPTION
GND
Ground pin for the ATIG outputs
PWR
Power supply for ATIG core, nominal 3.3V
Complementary clock of low-power differential push-pull PCI-Express pair with integrated series resistor. (no
OUT
50ohm shunt res istor to GND and no 33 ohm s eries resistor needed)
True clock of low-power differential push-pull PCI-Express pair with integrated series resistor. (no 50ohm shunt
OUT
resistor to GND and no 33 ohm series resistor needed)
Complementary clock of low-power differential push-pull PCI-Express pair with integrated series resistor. (no
OUT
50ohm shunt res istor to GND and no 33 ohm s eries resistor needed)
True clock of low-power differential push-pull PCI-Express pair with integrated series resistor. (no 50ohm shunt
OUT
resistor to GND and no 33 ohm series resistor needed)
PWR
Power supply for SATA core logic, nominal 3.3V
Complement clock of low power differential SRC/SATA clock pair. (no 50ohm shunt resistor to GND and no 33 ohm
OUT
s eries resistor needed
True clock of low power differential SRC/SATA cloc k pair. (no 50ohm shunt resistor to GND and no 33 ohm series
OUT
resistor needed
GND
Ground pin for the SRC outputs
GND
Ground for the Analog Core
PWR
3.3V Power for the Analog Core
Complementary signal of low-power differential push-pull AMD K8 "Greyhound" clock with integrated series
OUT
resistor.(no 33 ohm series resistor needed) / Complement clock of low power differential SRC clock pair. (no
50ohm shunt res istor to GND and no 33 ohm s eries resistor needed
True signal of low-power differential push-pull AMD K8 "Greyhound" cloc k with integrated series resistor. (no 33
OUT
ohm series resistor needed) / True clock of low power differential SRC clock pair. (no 50ohm shunt resistor to GND
and no 33 ohm s eries resistor needed
GND
Ground pin for the CPU outputs
PWR
Supply for CPU core, 3.3V nominal
Complementary signal of low-power differential push-pull AMD K8 "Greyhound" clock with integrated series resistor.
OUT
(no 33 ohm series resistor needed)
True signal of low-power differential push-pull AMD K8 "Greyhound" c lock with integrated series resistor.(no 33
OUT
ohm series resistor needed)
Enter /Exit Power Down.
IN
0 = Power Down, 1 = normal operation.
Open Drain I/O. As an input it restores the PLL's to power up default s tate. As an output, this signal is driven low
when the internal watchdog hardware timer expires. It is cleared when the internal watchdog hardware timer is reset
I/O
or disabled. The input is falling edge triggered.
0 = Restore Settings, 1 = normal operation.
PWR
Ground pin for the HTT outputs
Complementary signal of low-power differential push-pull hypertransport clock with integrated series resistor. (no
OUT
50ohm shunt res istor to GND and no 33 ohm s eries resistor needed) / 3.3V single ended 66MHz hyper transport
c lock
OUT
PWR
I/O
I/O
I/O
PWR
GND
IN
OUT
PWR
True signal of low-power differential push-pull hypertransport clock with integrated series resistor. (no 50ohm shunt
resistor to GND and no 33 ohm series resistor needed) / 3.3V single ended 66MHz hyper transport clock
Supply for HTT clocks , nominal 3.3V.
14.318 MHz 3.3V reference clock./ SEl_OC_MODE: latched input to select pin functionality
1 = ATIG/SRC PCIE Gen1 Mode with higher overclock ing ability
0 = ATIG/SRC PCIE Gen2 Mode with limited overclocking ability
14.318 MHz 3.3V reference clock./ 3.3V tolerant latched input to select function of SRC6/SATA output
0 = 100MHz differential spreading SRC clock, 1 = 100MHz non-s preading differential SATA clock
14.318 MHz 3.3V reference clock./ 3.3V tolerant latched input to select Hyper Transport Clock Frequency.
0 = 100MHz differential HTT clock, 1 = 66MHz 3.3V single ended HTT clock
Ref, XTAL power supply, nominal 3.3V
Ground pin for the REF outputs.
Crystal input, nominally 14.318MHz
Crystal output, nominally 14.318MHz
Power pin for the 48MHz outputs and core. 3.3V
ATIG1C_LPRS
ATIG1T_LPRS
ATIG0C_LPRS
ATIG0T_LPRS
VDDSATA
SRC6C/SATAC_LPRS
SRC6T/SATAT_LPRS
GNDSATA
GNDA
VDDA
CPUKG1C_LPRS/SRC7C_LPRS
46
47
48
49
50
51
CPUKG1T_LPRS/SRC7T_LPRS
GNDCPU
VDDCPU
CPUKG0C_LPRS
CPUKG0T_LPRS
PD#
52
53
54
RESTORE#
GNDHTT
HTT0C_LPRS/66M
55
56
57
58
59
60
61
62
63
64
HTT0T_LPRS/66M
VDDHTT
REF2/SEL_OC_MODE**
REF1/SEL_SATA
REF0/SEL_HTT66
VDDREF
GNDREF
X1
X2
VDD48
IDT®
PROGRAMMABLE SYSTEM CLOCK CHIP FOR ATI RD790-K8
TM
BASED SYSTEMS
3
9LPRS477D
REV C 010715
9LPRS477D
PROGRAMMABLE SYSTEM CLOCK CHIP FOR ATI RD790-K8
TM
BASED SYSTEMS
Block Diagram
X1
X2
14.318MHz
REF
OSC
48MHz_(1:0)
Fixed PLL4
EXACT 48MHz
SEL_SATA
100MHz
SRC6/SATA
SS
PLL
SB_SRC
(-0.5% DWN SP)
800MHz
SS
PLL
SB_SRC/SRC
100MHz
SB_SRC(1:0)
SRC ZDB PLL
400 to 900 MHz
PWD @
600MHz/6
SRC(5:0)
SEL_HTT66
HTT_100T/66
HTT_100C/66
CPUKG(1:0)
HTT 100MHz
SS PLL
HTT 66MHz
200MHz
ATIG ZDB PLL
ATIG(3:0)
SEL_OC_MODE
SEL_DOC
PD#
SEL_HTT66
SEL_SATA
SMBCLK
SMBDAT
RESTORE#
MODE
Control
Logic
Power Groups
Pin Number
V DD
64
11, 1 6
25
39
34
44
48
56
60
GND
3
10, 17
24
42
28,33
43
47
53
61
Description
USB _48 outputs
SRC differential outputs
SB _SRC differential outputs
SRC/SATA differential output
ATIG differential outputs
Analog, P LL
CPUK G differential outputs
HTTCLK output
REF outputs
IDT®
PROGRAMMABLE SYSTEM CLOCK CHIP FOR ATI RD790-K8
TM
BASED SYSTEMS
4
9LPRS477D
REV C 010715
9LPRS477D
PROGRAMMABLE SYSTEM CLOCK CHIP FOR ATI RD790-K8
TM
BASED SYSTEMS
Differential Output Power Management Table
PD#
CLKREQ#
SMBus
Register OE
Enable
X
Enable
Disable
True output
Complement
Output
True output
Complement
Output
Free-Run
Running
Low/20K
Running
Low/20K
Running
Low
Running
Low
CLKREQ# Selected
Running
Low/20K
Low/20K
Low/20K
Running
Low
Low
Low
1
0
1
X
0
X
1
X
Note: 20K means 20Kohm Pull Down
Singled-ended Power Management Table
PD#
1
0
SMBus
Register OE
Enable
Enable
USB
Running
Low
REF0, 1
Running
Hi-Z
RE F2
Running
Hi-Z
Table1: CPU and HTT Frequency Selection Table
Byte 3
Bit4
Bit3
Bit2
Bit1
Bit0
CPU
(MHz)
CPU
CPU
CPU
CPU
CPU
FS4
FS3
FS2
FS1
FS0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
200.00
205.00
210.00
215.00
220.00
225.00
230.00
235.00
240.00
245.00
250.00
255.00
260.00
265.00
270.00
200.00
280.00
285.00
290.00
295.00
300.00
305.00
310.00
315.00
320.00
325.00
330.00
335.00
340.00
345.00
350.00
355.00
HTT
Single-ended
SEL_HTT66 = 1
HTT
Differential
SEL_HTT66 = 0
Spread
%
(B6b6=1
and
B3b5=1)
CPU
CPU
Output
OverClock %
Divider
0%
2%
5%
8%
10%
13%
15%
18%
20%
23%
25%
28%
30%
33%
35%
0%
40%
43%
45%
48%
50%
53%
55%
58%
60%
63%
65%
68%
70%
73%
75%
78%
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
VCO
(MHz)
400.00
410.00
420.00
430.00
440.00
450.00
460.00
470.00
480.00
490.00
500.00
510.00
520.00
530.00
540.00
400.00
560.00
570.00
580.00
590.00
600.00
610.00
620.00
630.00
640.00
650.00
660.00
670.00
680.00
690.00
700.00
710.00
66.67
68.33
70.00
71.67
73.33
75.00
76.67
78.33
80.00
81.67
83.33
85.00
86.67
88.33
90.00
66.67
93.33
95.00
96.67
98.33
100.00
101.67
103.33
105.00
106.67
108.33
110.00
111.67
113.33
115.00
116.67
118.33
100.00
102.50
105.00
107.50
110.00
112.50
115.00
117.50
120.00
122.50
125.00
127.50
130.00
132.50
135.00
100.00
140.00
142.50
145.00
147.50
150.00
152.50
155.00
157.50
160.00
162.50
165.00
167.50
170.00
172.50
175.00
177.50
IDT®
PROGRAMMABLE SYSTEM CLOCK CHIP FOR ATI RD790-K8
TM
BASED SYSTEMS
Depends on SB_SRC PLL. See Table 4.
5
9LPRS477D
REV C 010715
