Integrated
Circuit
Systems, Inc.
ICS9LPRS480
Programmable System Clock Chip for ATI RS780 - K8
TM
based Systems
Recommended Application:
ATI RS780 systems using AMD K8 processors
Output Features:
•
Integrated series resistors on all differential outputs.
•
1 - Greyhound compatible K8 CPU pairs
•
5 - low-power differential SRC pairs
•
2 - low-power differential chipset SouthBridge SRC pairs
•
1 - Selectable low-power differential 100MHz non-spread
SATA/ SRC output
•
1 - Selectable low-power differential SRC / 27MHz Single
Ended outputs
•
1 - Selectable HT3 100MHz low-power differential
hypertransport clock / HT66MHz Single Ended outputs
•
1 - 48MHz USB clock
•
3 - 14.318MHz Reference clock
•
2 - low-power differential ATIG pairs
•
5- Dedicated CLKREQ# pins
Pin Configuration
HTT0C_LPRS/66M
HTT0T_LPRS/66M
REF0/SEL_HTT66
REF1/SEL_SATA
CPUKG0C_LPRS
48 VDDCPU
47 VDDCPU_IO
46 GNDCPU
45 CLKREQ1#*
44 CLKREQ2#*
43 GNDSATA
42 SRC6T/SATAT_LPRS
41 SRC6C/SATAC_LPRS
40 VDDSATA
39 CLKREQ3#*
38 CLKREQ4#*
37 SB_SRC0T_LPRS
36 SB_SRC0C_LPRS
35 VDDSB_SRC
34 VDDSB_SRC_IO
33 GNDSB_SRC
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
GNDSRC
VDDSRC_IO
*CLKREQ0#
GNDATIG
VDDATIG_IO
VDDATIG
ATIG1C_LPRS
ATIG0C_LPRS
SB_SRC1C_LPRS
SB_SRC1T_LPRS
ATIG1T_LPRS
ATIG0T_LPRS
SRC1C_LPRS
SRC1T_LPRS
SRC0C_LPRS
SRC0T_LPRS
CPUKG0T_LPRS
Key Specifications:
•
CPU outputs cycle-to-cycle jitter < 150ps
•
SRC outputs cycle-to-cycle jitter < 125ps
•
SB_SRC outputs cycle-to-cycle jitter < 125ps
•
+/- 100ppm frequency accuracy on CPU, SRC, ATIG
•
0ppm frequency accuracy on 48MHz
Features/Benefits:
•
Power Saving Features:
Optional Separate supply rail for SRC low Voltage I/O
- ~33% power saving when 1.5V is used for this rail
•
Spread Spectrum for EMI reduction
•
Outputs may be disabled via SMBus
•
External crystal load capacitors for maximum
frequency accuracy
REF2/SEL_27
48MHz_0
GNDREF
VDDREF
GNDHTT
VDDHTT
VDD48
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
GND48 1
SMBCLK 2
SMBDAT 3
VDD 4
SRC7C_LPRS/27MHz_NS 5
SRC7T_LPRS/27MHz_SS 6
GND 7
SRC4C_LPRS 8
SRC4T_LPRS 9
GNDSRC 10
VDDSRC_IO 11
SRC3C_LPRS 12
SRC3T_LPRS 13
SRC2C_LPRS 14
SRC2T_LPRS 15
VDDSRC 16
ICS9LPRS480
1391D—02/02/09
*Other names and brands may be claimed as the property of others.
PD#
X2
X1
Integrated
Circuit
Systems, Inc.
ICS9LPRS480
MLF Pin Description
PIN #
1
2
3
4
5
PIN NAME
GND48
SMBCLK
SMBDAT
VDD27
SRC7C_LPRS/27MHz_NS
PIN TYPE
GND
IN
I/O
PWR
OUT
DESCRIPTION
Ground pin for the 48MHz outputs
Clock pin of SMBus circuitry, 5V tolerant.
Data pin for SMBus circuitry, 5V tolerant.
3.3V Power supply for SRC/27MHz output and 27MHz SS PLL
True clock of low power differential SRC clock pair. (no 50ohm shunt resistor to GND and no 33
ohm series resistor needed)/27MHz 3.3V Single-ended non-spread output for discrete graphics
Complement clock of low power differential SRC clock pair. (no 50ohm shunt resistor to GND
and no 33 ohm series resistor needed)/27MHz 3.3V Single-ended spreading output for discrete
graphics
Ground for the SRC/27MHz outputs
Complement clock of low power differential SRC clock pair. (no 50ohm shunt resistor to GND
and no 33 ohm series resistor needed)
True clock of low power differential SRC clock pair. (no 50ohm shunt resistor to GND and no 33
ohm series resistor needed)
Ground pin for the SRC outputs
Power supply for differential SRC outputs, nominal 1.05V to 3.3V
Complement clock of low power differential SRC clock pair. (no 50ohm shunt resistor to GND
and no 33 ohm series resistor needed)
True clock of low power differential SRC clock pair. (no 50ohm shunt resistor to GND and no 33
ohm series resistor needed)
Complement clock of low power differential SRC clock pair. (no 50ohm shunt resistor to GND
and no 33 ohm series resistor needed)
True clock of low power differential SRC clock pair. (no 50ohm shunt resistor to GND and no 33
ohm series resistor needed)
Supply for SRC core, 3.3V nominal
Power supply for differential SRC outputs, nominal 1.05V to 3.3V
Ground pin for the SRC outputs
Complement clock of low power differential SRC clock pair. (no 50ohm shunt resistor to GND
and no 33 ohm series resistor needed)
True clock of low power differential SRC clock pair. (no 50ohm shunt resistor to GND and no 33
ohm series resistor needed)
Complement clock of low power differential SRC clock pair. (no 50ohm shunt resistor to GND
and no 33 ohm series resistor needed)
True clock of low power differential SRC clock pair. (no 50ohm shunt resistor to GND and no 33
ohm series resistor needed)
Clock Request pin for SRC0 outputs. If output is selected for control, then that output is controlled
as follows:
0 = enabled, 1 = Low-Low
Ground pin for the ATIG outputs
Power supply for differential ATIG outputs, nominal 1.05V to 3.3V
Power supply for ATIG core, nominal 3.3V
Complementary clock of low-power differential push-pull PCI-Express pair with integrated series
resistor. (no 50ohm shunt resistor to GND and no 33 ohm series resistor needed)
True clock of low-power differential push-pull PCI-Express pair with integrated series resistor. (no
50ohm shunt resistor to GND and no 33 ohm series resistor needed)
Complementary clock of low-power differential push-pull PCI-Express pair with integrated series
resistor. (no 50ohm shunt resistor to GND and no 33 ohm series resistor needed)
True clock of low-power differential push-pull PCI-Express pair with integrated series resistor. (no
50ohm shunt resistor to GND and no 33 ohm series resistor needed)
Complement clock of low power differential Chipset-to-Chipset SRC clock pair. (no 50ohm shunt
resistor to GND and no 33 ohm series resistor needed
True clock of low power differential Chipset-to-Chipset SRC clock pair. (no 50ohm shunt resistor
to GND and no 33 ohm series resistor needed
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
SRC7T_LPRS/27MHz_SS
GND27
SRC4C_LPRS
SRC4T_LPRS
GNDSRC
VDDSRC_IO
SRC3C_LPRS
SRC3T_LPRS
SRC2C_LPRS
SRC2T_LPRS
VDDSRC
VDDSRC_IO
GNDSRC
SRC1C_LPRS
SRC1T_LPRS
SRC0C_LPRS
SRC0T_LPRS
*CLKREQ0#
GNDATIG
VDDATIG_IO
VDDATIG
ATIG1C_LPRS
ATIG1T_LPRS
ATIG0C_LPRS
ATIG0T_LPRS
SB_SRC1C_LPRS
SB_SRC1T_LPRS
OUT
GND
OUT
OUT
GND
PWR
OUT
OUT
OUT
OUT
PWR
PWR
GND
OUT
OUT
OUT
OUT
IN
GND
PWR
PWR
OUT
OUT
OUT
OUT
OUT
OUT
1391D—02/02/09
2
Integrated
Circuit
Systems, Inc.
ICS9LPRS480
MLF Pin Description (Continued)
PIN #
PIN NAME
33 GNDSB_SRC
34 VDDSB_SRC_IO
35 VDDSB_SRC
36
37
38
SB_SRC0C_LPRS
SB_SRC0T_LPRS
CLKREQ4#*
PIN TYPE
DESCRIPTION
GND
Ground pin for the SB_SRC outputs
PWR
Power supply for differential SB_SRC outputs, nominal 1.05V to 3.3V
PWR
Supply for SB SRC PLL core, 3.3V nominal
Complement clock of low power differential Chipset-to-Chipset SRC clock pair. (no 50ohm shunt
OUT
resistor to GND and no 33 ohm series resistor needed
True clock of low power differential Chipset-to-Chipset SRC clock pair. (no 50ohm shunt resistor
OUT
to GND and no 33 ohm series resistor needed
Clock Request pin for SRC4 outputs. If output is selected for control, then that output is controlled
IN
as follows:
0 = enabled, 1 = Low-Low
Clock Request pin for SRC3 outputs. If output is selected for control, then that output is controlled
IN
as follows:
0 = enabled, 1 = Low-Low
PWR
Power supply for SATA core logic, nominal 3.3V
Complement clock of low power differential SRC/SATA clock pair. (no 50ohm shunt resistor to
OUT
GND and no 33 ohm series resistor needed)
True clock of low power differential SRC clock pair. (no 50ohm shunt resistor to GND and no 33
OUT
ohm series resistor needed)
GND
Ground pin for the SRC outputs
Clock Request pin for SRC2 outputs. If output is selected for control, then that output is controlled
IN
as follows:
0 = enabled, 1 = Low-Low
Clock Request pin for SRC1 outputs. If output is selected for control, then that output is controlled
IN
as follows:
0 = enabled, 1 = Low-Low
GND
Ground pin for the CPU outputs
PWR
Power supply for differential CPU outputs, nominal 1.05V to 3.3V
PWR
Supply for CPU core, 3.3V nominal
Complementary signal of low-power differential push-pull AMD K8 "Greyhound" clock with
OUT
integrated series resistor. (no 33 ohm series resistor needed)
True signal of low-power differential push-pull AMD K8 "Greyhound" clock with integrated series
OUT
resistor.(no 33 ohm series resistor needed)
Enter /Exit Power Down.
IN
0 = Power Down, 1 = normal operation.
PWR
Ground pin for the HTT outputs
Complementary signal of low-power differential push-pull hypertransport clock with integrated
series resistor. (no 50ohm shunt resistor to GND and no 33 ohm series resistor needed) / 1.8V
OUT
single ended 66MHz hyper transport clock
True signal of low-power differential push-pull hypertransport clock with integrated series
OUT
resistor. (no 50ohm shunt resistor to GND and no 33 ohm series resistor needed) /1.8V single
ended 66MHz hyper transport clock
PWR
Supply for HTT clocks, nominal 3.3V.
PWR
Ref, XTAL power supply, nominal 3.3V
I/O
14.318 MHz reference clock, 3.3V/3.3V Latched input to select 27MHz SS and non SS on SRC7
0 = 100MHz differential spreading SRC clock, 1 = 27MHz non-spreading singled clock on pin 5
and 27MHz spread clock on pin 6.
14.318 MHz 3.3V reference clock./ 3.3V tolerant latched input to select function of SRC6/SATA
output
0 = 100MHz differential spreading SRC clock, 1 = 100MHz non-spreading differential SATA clock
14.318 MHz 3.3V reference clock./ 3.3V tolerant latched input to select Hyper Transport Clock
Frequency.
0 = 100MHz differential HTT clock, 1 = 66MHz 3.3V single ended HTT clock
Ground pin for the REF outputs.
Crystal input, nominally 14.318MHz
Crystal output, nominally 14.318MHz
Power pin for the 48MHz outputs and core. 3.3V
48MHz clock output.
39
40
41
42
43
44
CLKREQ3#*
VDDSATA
SRC6C/SATAC_LPRS
SRC6T/SATAT_LPRS
GNDSATA
CLKREQ2#*
45
46
47
48
49
50
51
52
53
CLKREQ1#*
GNDCPU
VDDCPU_IO
VDDCPU
CPUKG0C_LPRS
CPUKG0T_LPRS
PD#
GNDHTT
HTT0C_LPRS/66M
54
55
56
57
HTT0T_LPRS/66M
VDDHTT
VDDREF
REF2/SEL_27
58
REF1/SEL_SATA
I/O
59
60
61
62
63
64
REF0/SEL_HTT66
GNDREF
X1
X2
VDD48
48MHz_0
I/O
GND
IN
OUT
PWR
OUT
1391D—02/02/09
3
Integrated
Circuit
Systems, Inc.
ICS9LPRS480
Pin Configuration
REF1/SEL_SATA
REF0/SEL_HTT66
GNDREF
X1
X2
VDD48
48MHz_0
GND48
SMBCLK
SMBDAT
VDD27
SRC7C_LPRS/27MHz_NS
SRC7T_LPRS/27MHz_SS
GND27
SRC4C_LPRS
SRC4T_LPRS
GNDSRC
VDDSRC_IO
SRC3C_LPRS
SRC3T_LPRS
SRC2C_LPRS
SRC2T_LPRS
VDDSRC
VDDSRC_IO
GNDSRC
SRC1C_LPRS
SRC1T_LPRS
SRC0C_LPRS
SRC0T_LPRS
*CLKREQ0#
GNDATIG
VDDATIG_IO
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
REF2/SEL_27
VDDREF
VDDHTT
HTT0T_LPRS/66M
HTT0C_LPRS/66M
GNDHTT
PD#
CPUKG0T_LPRS
CPUKG0C_LPRS
VDDCPU
VDDCPU_IO
GNDCPU
CLKREQ1#*
CLKREQ2#*
GNDSATA
SRC6T/SATAT_LPRS
SRC6C/SATAC_LPRS
VDDSATA
CLKREQ3#*
CLKREQ4#*
SB_SRC0T_LPRS
SB_SRC0C_LPRS
VDDSB_SRC
VDDSB_SRC_IO
GNDSB_SRC
SB_SRC1T_LPRS
SB_SRC1C_LPRS
ATIG0T_LPRS
ATIG0C_LPRS
ATIG1T_LPRS
ATIG1C_LPRS
VDDATIG
64-Pin TSSOP
* Internal Pull-Up Resistor
** Internal Pull-Down Resistor
1391D—02/02/09
4
ICS9LPRS480
Integrated
Circuit
Systems, Inc.
ICS9LPRS480
TSSOP Pin Description
PIN #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
PIN NAME
REF1/SEL_SATA
REF0/SEL_HTT66
GNDREF
X1
X2
VDD48
48MHz_0
GND48
SMBCLK
SMBDAT
VDD27
SRC7C_LPRS/27MHz_NS
SRC7T_LPRS/27MHz_SS
GND27
SRC4C_LPRS
SRC4T_LPRS
GNDSRC
VDDSRC_IO
SRC3C_LPRS
SRC3T_LPRS
SRC2C_LPRS
SRC2T_LPRS
VDDSRC
VDDSRC_IO
GNDSRC
SRC1C_LPRS
SRC1T_LPRS
SRC0C_LPRS
SRC0T_LPRS
*CLKREQ0#
GNDATIG
VDDATIG_IO
PIN TYPE
I/O
I/O
GND
IN
OUT
PWR
OUT
GND
IN
I/O
PWR
OUT
OUT
GND
OUT
OUT
GND
PWR
OUT
OUT
OUT
OUT
PWR
PWR
GND
OUT
OUT
OUT
OUT
IN
GND
PWR
DESCRIPTION
14.318 MHz 3.3V reference clock./ 3.3V tolerant latched input to select function of SRC6/SATA output
0 = 100MHz differential spreading SRC clock, 1 = 100MHz non-spreading differential SATA clock
14.318 MHz 3.3V reference clock./ 3.3V tolerant latched input to select Hyper Transport Clock
Frequency.
0 = 100MHz differential HTT clock, 1 = 66MHz 3.3V single ended HTT clock
Ground pin for the REF outputs.
Crystal input, nominally 14.318MHz
Crystal output, nominally 14.318MHz
Power pin for the 48MHz outputs and core. 3.3V
48MHz clock output.
Ground pin for the 48MHz outputs
Clock pin of SMBus circuitry, 5V tolerant.
Data pin for SMBus circuitry, 5V tolerant.
3.3V Power supply for SRC/27MHz output and 27MHz SS PLL
True clock of low power differential SRC clock pair. (no 50ohm shunt resistor to GND and no 33 ohm
series resistor needed)/27MHz 3.3V Single-ended non-spread output for discrete graphics
Complement clock of low power differential SRC clock pair. (no 50ohm shunt resistor to GND and no 33
ohm series resistor needed)/27MHz 3.3V Single-ended spreading output for discrete graphics
Ground for the SRC/27MHz outputs
Complement clock of low power differential SRC clock pair. (no 50ohm shunt resistor to GND and no 33
ohm series resistor needed)
True clock of low power differential SRC clock pair. (no 50ohm shunt resistor to GND and no 33 ohm
series resistor needed)
Ground pin for the SRC outputs
Power supply for differential SRC outputs, nominal 1.05V to 3.3V
Complement clock of low power differential SRC clock pair. (no 50ohm shunt resistor to GND and no 33
ohm series resistor needed)
True clock of low power differential SRC clock pair. (no 50ohm shunt resistor to GND and no 33 ohm
series resistor needed)
Complement clock of low power differential SRC clock pair. (no 50ohm shunt resistor to GND and no 33
ohm series resistor needed)
True clock of low power differential SRC clock pair. (no 50ohm shunt resistor to GND and no 33 ohm
series resistor needed)
Supply for SRC core, 3.3V nominal
Power supply for differential SRC outputs, nominal 1.05V to 3.3V
Ground pin for the SRC outputs
Complement clock of low power differential SRC clock pair. (no 50ohm shunt resistor to GND and no 33
ohm series resistor needed)
True clock of low power differential SRC clock pair. (no 50ohm shunt resistor to GND and no 33 ohm
series resistor needed)
Complement clock of low power differential SRC clock pair. (no 50ohm shunt resistor to GND and no 33
ohm series resistor needed)
True clock of low power differential SRC clock pair. (no 50ohm shunt resistor to GND and no 33 ohm
series resistor needed)
Clock Request pin for SRC0 outputs. If output is selected for control, then that output is controlled as
follows:
0 = enabled, 1 = Low-Low
Ground pin for the ATIG outputs
Power supply for differential ATIG outputs, nominal 1.05V to 3.3V
1391D—02/02/09
5
