Datasheet
PROGRAMMABLE TIMING CONTROL HUB FOR
INTEL BASED SYSTEMS
Recommended Application:
CK505 version 1.1 clock, with fully integrated voltage regulators
and series resistors
ICS9LRS3187B
Features/Benefits:
•
•
•
•
Supports spread spectrum modulation, 0 to -0.5%
down spread for CPU and SRC clocks
Uses external 14.318MHz crystal, external crystal load
caps are required for frequency tuning
Available in commercial (0 to +70°C) and industrial
(-40 to +85°C) temperature ranges
Meets PCIe Gen2 specifications
Output Features:
•
•
•
•
•
•
2 - CPU differential low power push-pull pairs
1 - SRC differential low power push-pull pair
1 - SATA differential low power push-pull pair
1 - DOT differential low power push-pull pair
1 - REF, able to drive 3 loads, 14.318MHz
1 - 27MHz_SS/non_SS single-ended output pair
Key Specifications:
•
•
•
CPU outputs cycle-cycle jitter <85ps
SRC outputs cycle-cycle jitter <125ps
+/- 100ppm frequency accuracy on all clocks
32 31 30 29 28 27 26 25
VDDDOT96MHz_3.3 1
GNDDOT96MHz 2
DOT96T_LPR 3
DOT96C_LPR 4
VDD_27MHz 5
27MHz_nonSS 6
27MHz_SS 7
GND27MHz 8
9 10 11 12 13 14 15 16
SATAT_LPR
SATAC_LPR
SRCT1_LPR
*CPU_STOP#
SRCC1_LPR
VDDSRC_IO
GNDSATA
GNDSRC
24 VDDCPU_3.3
23 CPUT0_LPR
22 CPUC0_LPR
21 GNDCPU
20 CPUT1_LPR
19 CPUC1_LPR
18 VDDCPU_IO
17 VDDSRC_3.3
9LRS3187
** Internal Pull-Down Resistor
* Internal Pull-Up Resistor
32-pin MLF
IDT
®
Programmable Timing Control Hub for Intel Based Systems
1602F—11/04/11
1
CLKPWRGD/PD#_3.3
REF_2L/FSLC_3.3**
Pin Configuration
VDDREF_3.3
SDATA_3.3
SCLK_3.3
GNDREF
X1
X2
ICS9LRS3187B
Programmable Timing Control Hub for Intel Based Systems
Datasheet
Pin Description
Pin# Pin Name
1
2
3
4
5
6
7
8
9
10
VDDDOT96MHz_3.3
GNDDOT96MHz
DOT96T_LPR
DOT96C_LPR
VDD_27MHz
27MHz_nonSS
27MHz_SS
GND27MHz
GNDSATA
SATAT_LPR
Type Pin Description
PWR Power pin for the 96MHz output 3.3V.
PWR Ground pin for the 96MHz output
True DOT96 output with integrated 33ohm series resistor. No
OUT
50ohm resistor to GND needed.
Complement DOT96 output with integrated 33ohm series
OUT
resistor. No 50ohm resistor to GND needed.
PWR Power pin for the 27MHz output 3.3V.
OUT
OUT
OUT
3.3V Single-ended 27MHz non-spread clock.
3.3V Single-ended 27MHz spread clock.
Ground pin for the 27MHz outputs.
11
12
13
SATAC_LPR
GNDSRC
SRCT1_LPR
14
15
16
17
18
19
SRCC1_LPR
VDDSRC_IO
*CPU_STOP#
VDDSRC_3.3
VDDCPU_IO
CPUC1_LPR
PWR Ground pin for the SATA outputs.
True clock of differential 0.8V push-pull SATA/SRC output with
OUT integrated 33ohm series resistor. No 50ohm resistor to GND
needed.
Complementary clock of differential 0.8V push-pull SATA/SRC
OUT output with integrated 33ohm series resistor. No 50ohm resistor
to GND needed.
PWR Ground pin for the SRC outputs
True clock of differential 0.8V push-pull SRC output with
OUT integrated 33ohm series resistor. No 50ohm resistor to GND
needed.
Complementary clock of differential 0.8V push-pull SRC output
OUT with integrated 33ohm series resistor. No 50ohm resistor to
GND needed.
PWR 1.05V to 3.3V from external power supply
Stops all CPU clocks, except those set to be free running
IN
clocks
PWR Supply for SRC clocks, 3.3V nominal
PWR 1.05V to 3.3V from external power supply
Complementary clock of differential pair 0.8V push-pull CPU
OUT outputs with integrated 33ohm series resistor. No 50 ohm
resistor to GND needed.
True clock of differential pair 0.8V push-pull CPU outputs with
OUT integrated 33ohm series resistor. No 50 ohm resistor to GND
needed.
PWR Ground pin for the CPU outputs.
Complementary clock of differential pair 0.8V push-pull CPU
OUT outputs with integrated 33ohm series resistor. No 50 ohm
resistor to GND needed.
True clock of differential pair 0.8V push-pull CPU outputs with
OUT integrated 33ohm series resistor. No 50 ohm resistor to GND
needed.
PWR Supply for CPU clocks, 3.3V nominal
IN
OUT
IN
Notifies CK505 to sample latched inputs, or PWRDWN# mode
Crystal output, Nominally 14.318MHz
Crystal input, Nominally 14.318MHz
PWR Ground pin for the REF outputs.
20
21
22
CPUT1_LPR
GNDCPU
CPUC0_LPR
23
24
25
26
27
28
29
30
31
32
CPUT0_LPR
VDDCPU_3.3
CLKPWRGD/PD#_3.3
GNDREF
X2
X1
VDDREF_3.3
REF_2/FSLC_3.3**
SDATA_3.3
SCLK_3.3
PWR Power pin for the XTAL and REF clocks, nominal 3.3V
14.318 MHz reference clock, which can drive 2 loads / 3.3V
I/O tolerant input for CPU frequency selection. Refer to input
electrical characteristics for Vil_FS and Vih_FS values.
I/O Data pin for SMBus circuitry, 3.3V tolerant
IN
Clock pin of SMBus circuitry, 3.3V tolerant.
1602F—11/04/11
IDT
®
Programmable Timing Control Hub for Intel Based Systems
2
ICS9LRS3187B
Programmable Timing Control Hub for Intel Based Systems
Datasheet
General Description
The
ICS9LRS3187B
is a CK505 clock synthesizer. The
ICS9LRS3187B
provides a single-chip solution for Intel based systems.
The
ICS9LRS3187B
is driven with a 14.318MHz crystal.
Functional Block Diagram
14.318M
Xtal
REFCLK
SS PLL
27MHz_SS
SS PLL
PLL
SRC
CPUCLK
SRC(1)
CPUCLK(1:0)
0
SATA_nonSS
SATA
1
B0b1
COUT_DIV
Non-SS
PLL
27MHz nonSS
DOT96MHz
Table: Power Distribution
Ground VDD_IO VDD 3.3V
2
8
9
12
21
26
1
5
17
17
24
29
Output
DOT96
27M
SATA
SRC
CPU
REF
15
15
18
IDT
®
Programmable Timing Control Hub for Intel Based Systems
1602F—11/04/11
3
ICS9LRS3187B
Programmable Timing Control Hub for Intel Based Systems
Datasheet
Table 1: CPU Frequency Select Table
FS
L
C
B0b7
0 (Default)
1
CPU
MHz
133.33
100.00
SRC
MHz
100.00
REF
MHz
14.318
DOT
MHz
96.00
1. FS
L
C is a low-threshold input.Please see V
IL_FS
and V
IH_FS
specifications in
the Input/Supply/Common Output Parameters Table for correct values.
Also refer to the Test Clarification Table.
Table 2: pin 6, 7 Configuration
B1b3
0
0
0
0
1
1
1
1
B1b2
0
0
1
1
0
0
1
1
B1b1
0
1
0
1
0
1
0
1
Pin 6
MHz
Pin 7
MHz
Spread
%
Comment
27MHz_nonSS
27MHz_nonSS
27MHz_nonSS
27MHz_nonSS
27MHz_nonSS
27MHz_nonSS
27MHz_nonSS
27MHz_nonSS
27MHz_SS
27MHz_SS
27MHz_SS
27MHz_SS
27MHz_SS
27MHz_SS
27MHz_SS
27MHz_SS
-1.75%
+-0.5%
-0.5%
-1%
-1.5%
-2%
-0.75%
-1.25%
Default
Table 3: IO_Vout select table
B9b2
0
0
0
0
1
1
1
1
B9b1
0
0
1
1
0
0
1
1
B9b0
0
1
0
1
0
1
0
1
IO_Vout
0.3V
0.4V
0.5V
0.6V
0.7V
0.8V
0.9V
1.0V
IDT
®
Programmable Timing Control Hub for Intel Based Systems
1602F—11/04/11
4
ICS9LRS3187B
Programmable Timing Control Hub for Intel Based Systems
Datasheet
CPU Power Management Table
SMBus
PD# CPU_STOP#
CPU1
Reg. OE
1
Enable
Running
1
X
Enable
Low/20K
0
1
Enable
High
0
1
X
Low/20K
Disable
M1
Running
CPU1#
Running
Low
Low
Low
Running
CPU0
Running
Low/20K
High
Low/20K
Low/20K
CPU0#
Running
Low
Low
Low
Low
SRC and DOT96MHz Power Management Table
PD# CPU_STOP#
0
1
1
X
X
X
M1
SMBus
Reg. OE
Enable
Enable
Disable
SRC
Low/20K
Running
Low/20K
Low/20K
SRC#
Low
Running
Low
Low
DOT
Low/20K
Running
Low/20K
Low/20K
DOT#
Low
Running
Low
Low
Singled-ended Power Management Table
SMBus
PD# CPU_STOP#
27M
Reg. OE
1
X
Enable
Running
X
Enable
Low
0
1
X
Low
Disable
M1
Low
REF
Running
Hi-Z
Low
Hi-Z
IDT
®
Programmable Timing Control Hub for Intel Based Systems
1602F—11/04/11
5
