DATASHEET
LOW POWER PROGRAMMABLE TIMING CONTROL HUB
TM
FOR INTEL SYSTEMS
9LRS4206
General Description
The 9LRS4206 is a low power CK505-compliant clock
specification. This clock synthesizer provides a single chip
solution for Intel processors and Intel chipsets. The
9LRS4206 is driven with a 14.318MHz crystal.
Features/Benefits
•
Supports tight ppm accuracy clocks for Serial-ATA and
•
•
•
•
•
•
•
•
•
•
PCIEX
Supports programmable spread percentage and
frequency
Uses external 14.318MHz crystal, external crystal load
caps are required for frequency tuning
Low power differential clock outputs (No 50 resistor to
GND needed)
Integrated 33 series resistor on all differential outputs
Meets PCIEX Gen2 Specification
Recommended Application
Low Power CK505 Compliant Main Clock
Output Features
•
•
•
•
•
•
1 - 0.8V push-pull differential CPU pair
1- 0.8V push-pull differential PCIEX pair
1 - 0.8V push-pull differential SATA pair
1 - 0.8V push-pull differential DOT96 pair
1 - USB, 48MHz
1 - REF, 14.318MHz
Key Specifications
CPU outputs cycle-cycle jitter < 85ps
PCIEX outputs cycle-cycle jitter < 125ps
SATA outputs cycle-cycle jitter < 125ps
±100ppm frequency accuracy on CPU, PCIEX and SATA
clocks
±100ppm frequency accuracy on USB clocks
Block Diagram
USB48MHz
Fixed PLL
X1
X2
XTAL
Frequency
Dividers
DOT96T_LR
DOT96C_LR
REF
CPUT_LR
SCLK
SDATA
FSLA
FSLB
FSLC
VTTPWRG/PD#
RLATCH
CPUC_LR
PLL Array
Control
Logic
Programmable
Frequency
Divider Array
STOP
Logic
PCIEXT_LR
PCIEXC_LR
SATAT_LR
SATAC_LR
Preferred drive strengths using CK505 clock sources.
Transmission lines to load do not share series resistors.
Desktop (Zo=50Ω) and mobile (Zo=55Ω) have the same drive strength.
Number of Loads
to Drive
D.C.Drive Strength
1
2
3
Number of Loads Actually Driven.
Match Point for N
& P Voltage /
1 Load Rs = 2 Loads Rs= 3 Loads Rs =
Current (mA)
0.56 / 33
(17Ω)
0.92 / 66
(14Ω)
1.15 / 99
(11.6Ω)
33Ω [39Ω]
39
Ω
[43
Ω
]
43
Ω
[43
Ω
]
-
22
Ω
[27
Ω
]
27
Ω
[33
Ω
]
-
-
15
Ω
[22
Ω
]
IDT®
LOW POWER PROGRAMMABLE TIMING CONTROL HUB
TM
FOR INTEL SYSTEMS
1
9LRS4206
REV A 012814
9LRS4206
LOW POWER PROGRAMMABLE TIMING CONTROL HUB
TM
FOR INTEL SYSTEMS
Pin Configuration
REF/FSLC
RLATCH**
GNDREF
VDDREF
25
24 SDATA
23 SCLK
22 GNDCPU
21 CPUT_LR
20 CPUC_LR
19 VDDCPU
18 RESET_IN#/RESET_OUT#*
17 AGND
9
VDDSATA
10
SATAT_LR
11
SATAC_LR
12
VDDA_FIX
13
GNDPCIEX
14
PCIEXC_LR
15
PCIEXT_LR
16
VDDA
GND
VDD
X1
27
X2
26
32
VDD 1
VTTPWRG/PD# 2
VDD96 3
USB48M/FSLA 4
GND96 5
DOT96T_LR 6
DOT96C_LR 7
FSLB 8
31
30
29
28
9LRS4206
* Internal Pull-Up Resistor
** Internal Pull-Down Resistor
32-Pin MLF
Functionality Table
FS
L
C FS
L
B FS
L
A
(B0b2) (B0b1) (B0b0)
0
0
1
1
0
1
CPU
MHz
133.33
100.00
PCIEX
MHz
100.00
100.00
SATA
MHz
100.00
100.00
DOT96
MHz
96.00
96.00
CPU/PCIEX PLL Spread Frequency Selection Table
FS
L
C FS
L
B FS
L
A
(B0b2) (B0b1) (B0b0)
0
0
1
1
0
1
CPU
MHz
133.33
100.00
PCIEX
MHz
100.00
100.00
SATA
MHz
100.00
100.00
Spread %
(B0b5=1)
0.5% Down
0.5% Down
Power Management Table
PD#
1
0
1
SMBus Register
OE
Enable
Enable
Disable
CPUT/C
Running
Low
Low
PCIEXT/C DOT96T/C SATAT/C
Runni ng
Lo w
Lo w
Running
Low
Low
Running
Low
Low
48M
Running
Low
Low
REF
Running
Low
Low
9LRS4206 Power Distribution Table
VDD Pin#
1
3
9
12
16
19
25
30
GND Pin#
5
5
13
5
17
22
28
32
Description
CPU PLL digital
48MHz output
SATACLK output
Fix PLL analog
CPU PLL core; PC IEX output; CPU PLL analog
CPUCLK output
Fix PLL digital; REF output
Fix PLL core
2
9LRS4206
REV A 012814
IDT®
LOW POWER PROGRAMMABLE TIMING CONTROL HUB
TM
FOR INTEL SYSTEMS
9LRS4206
LOW POWER PROGRAMMABLE TIMING CONTROL HUB
TM
FOR INTEL SYSTEMS
Pin Descriptions
PIN #
1
VDD
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
PIN NAME
TYPE
PWR Power supply, nominal 3.3V
IN
PWR
I/O
PWR
OUT
OUT
IN
PWR
OUT
OUT
PWR
PWR
OUT
OUT
PWR
PWR
I/O
PWR
OUT
OUT
PWR
IN
I/O
PWR
OUT
IN
PWR
I/O
PWR
IN
PWR
DESCRIPTION
This active high 3.3V LVTTL input is a level sensitive strobe used to determine
when latch inputs are valid and are ready to be sampled / Asynchronous active
low input pin that is used to power down the device into low power state.
Power supply for DOT96 outputs.
3.3V tolerant input for CPU frequency selection. Refer to input electrical
characteristics for Vil_FS and Vih_FS values / Fixed 3.3V 48MHz USB clock
output.
Ground pin for DOT96 outputs.
True clock of DOT 96MHz low power differential output pair with integrated
33ohm series resistor and no 50ohm to GND needed
Complement clock of DOT 96MHz low power differential output pair with
integrated 33ohm series resistor and no 50ohm to GND needed
3.3V tolerant input for CPU frequency selection. Refer to input electrical
characteristics for Vil_FS and Vih_FS values.
Power supply for SATA clocks, nominal 3.3V
True clock of 0.8V push-pull differential SATA pair with integrated 33ohm series
resistor and no 50ohm to GND needed
Complement clock of 0.8V push-pull differential SATA pair with integrated 33ohm
series resistor and no 50ohm to GND needed
Power supply for FIX PLL Analog, nominal 3.3V.
Ground pin for PCIEX outputs.
Complement clock of 0.8V differential push-pull PCI_Express pair with integrated
33ohm series resistor and no 50ohm to GND needed
True clock of 0.8V differential push-pull PCI_Express pair with integrated 33ohm
series resistor and no 50ohm to GND needed
3.3V power for the PLL core.
Ground pin for the PLL core.
Real time active low input. When active, SMBus is reset to power up default /
Real time system reset signal for frequency gear ratio change or watchdog timer
timeout. This signal is active low.
Supply for CPU clocks, 3.3V nominal
Complementary clock of differential pair 0.8V push-pull CPU outputs with
integrated 33ohm series resistor and no 50ohm to GND needed
True clock of differential pair 0.8V push-pull CPU outputs with integrated 33ohm
series resistor and no 50ohm to GND needed
Ground pin for CPU outputs.
Clock pin of SMBus circuitry, 3.3V tolerant.
Data pin for SMBus circuitry, 3.3V tolerant.
Ref, XTAL power supply, nominal 3.3V
Crystal output, Nominally 14.318MHz
Crystal input, Nominally 14.318MHz.
Ground for REF outputs.
14.318 MHz reference clock./ 3.3V tolerant input for CPU frequency selection.
Refer to input electrical characteristics for Vil_FS and Vih_FS values.
Power supply, nominal 3.3V
Asynchronous input pin used in combination with VTTPWRGD signal to
determine whether to reset SMBus.
Ground pin.
VTTPWRG/PD#
VDD96
USB48M/FSLA
GND96
DOT96T_LR
DOT96C_LR
FSLB
VDDSATA
SATAT_LR
SATAC_LR
VDDA_FIX
GNDPCIEX
PCIEXC_LR
PCIEXT_LR
VDDA
AGND
RESET_IN#/RESET_OUT#*
VDDCPU
CPUC_LR
CPUT_LR
GNDCPU
SCLK
SDATA
VDDREF
X2
X1
GNDREF
REF/FSLC
VDD
RLATCH**
GND
IDT®
LOW POWER PROGRAMMABLE TIMING CONTROL HUB
TM
FOR INTEL SYSTEMS
3
9LRS4206
REV A 012814
9LRS4206
LOW POWER PROGRAMMABLE TIMING CONTROL HUB
TM
FOR INTEL SYSTEMS
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the 9LRS4206. These ratings, which are standard
values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other
conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over
the recommended operating temperature range.
PARAMETER
SYMBOL
CONDITIONS
MIN
Maximum Supply Voltage
VDDxxx
Core/Logic Supply
V
IH
3.3V LVC MOS Inputs
Maximum Input Voltage
Minimum Input Voltage
V
IL
Any Input
GN D - 0.5
Storage Temperature
Ts
-
-65
Case Temperature
Tcase
-
Input ESD protection
ESD prot
Human Body Model
2000
1
U nless otherw ise noted, guaranteed by design and characterization, not 100% tested in production.
2
Operation under these conditions is neither implied, nor guaranteed.
3
Maximum input voltage is not to exceed maximum VDD
MAX
4.6
4.6
150
115
UNITS
V
V
V
C
°C
V
°
Notes
1,2
1,2,3
1,2
1,2
1,2
1,2
Electrical Characteristics–Input/Supply/Common Output Parameters
PARAMETER
Ambient Operating Temp
Supply Voltage
Input High Voltage
Input Low Voltage
Low Threshold Input-
High Voltage
Low Threshold Input-
Low Voltage
Input Leakage Current
Input Leakage Current
Output High Voltage
Output Low Voltage
Operating Supply Current
Powerdown Current
Input Frequency
Pin Inductance
Input Capacitance
SYMBOL
Tambient
VDDxxx
V
IHSE
V
ILSE
V
IH_F S
V
IL _FS
I
IN
I
INRE S
V
OHSE
V
OLSE
I
DD OP3.3
I
D DPD 3.3
F
i
L
pin
C
IN
C
OUT
C
IN X
CONDITIONS
-
Supply Voltage
Single-ended inputs
Single-ended inputs
3.3 V +/-5%
3.3 V +/-5%
V
I N
= V
D D ,
V
I N
= GND
Inputs with pull or pull down resistors
V
I N
= V
D D ,
V
I N
= GND
Single-ended outputs, I
OH
= -1mA
Single-ended outputs, I
OL
= 1 mA
Full Active, C
L
= Full load; ID D 3.3V
Power dow n mode, 3.3V Rail
V
D D
= 3.3 V
Logic Inputs
Output pin capacitance
X1 & X2 pins
MIN
0
3.135
2
V
SS
- 0.3
0.7
V
SS
- 0.3
-5
-200
2.4
0.4
125
5
15
7
5
6
6
33
MAX
70
3.465
V
D D
+ 0.3
0.8
VDD +0.3
0.35
5
200
UNITS
°C
V
V
V
V
V
uA
uA
V
V
mA
mA
MHz
nH
pF
pF
pF
kHz
Notes
1,4
1,4
1
1
1,3
1
1,2
1,2
1
1
1
1
1
1
1
1
1.5
Spread Spectrum
f
SSM OD
Triangular Modulation
30
Modulation Frequency
*TA = 0 - 70°C; Supply Voltage VD D = 3.3 V +/-5%
1
U nless otherw ise noted, guaranteed by design and characterization, not 100% tested in production.
2
Signal is required to be monotonic in this region.
3
4
Input leakage current does not include inputs with pull-up or pull-down resistors
3.3V referenced inputs are: RESET_IN, RLATCH, SCLK, SDATA, VTTWRGD inputs if selected.
IDT®
LOW POWER PROGRAMMABLE TIMING CONTROL HUB
TM
FOR INTEL SYSTEMS
4
9LRS4206
REV A 012814
9LRS4206
LOW POWER PROGRAMMABLE TIMING CONTROL HUB
TM
FOR INTEL SYSTEMS
Electrical Characteristics–SMBus Interface
PARAMETER
SYMBOL
CONDITIONS
MIN
V
DD
2.7
SMBus Voltage
V
OLSMB
@ I
PULLU P
Low-level Output Voltage
Current sinking at
SMB Data Pin
4
I
PULLU P
V
OLSMB
= 0.4 V
SC LK/SDATA
(Max VIL - 0.15) to
T
RI2C
C lock/Data Rise Time
(Min VIH + 0.15)
(Min VIH + 0.15) to
SCLK/SDATA
T
F I2C
(Max VIL - 0.15)
Clock/Data Fall Time
Maximum SMBus
F
SMBUS
Block Mode
Operating Frequency
1
U nless otherw ise noted, guaranteed by design and characterization, not 100% tested in production.
MAX
5.5
0.4
UNITS
V
V
mA
1000
300
100
ns
ns
kHz
Notes
1
1
1
1
1
1
AC Electrical Characteristics–Input/Common Parameters
PARAMETER
Clk Stabilization
Tdrive_PD#
SYMBOL
T
ST AB
T
D RPD
CONDITIONS
From VDD Power-Up or de-assertion of
PD# to 1st clock
Differential output enable after
PD# de-assertion
MIN
MAX
1.8
300
5
5
UNITS
ms
us
ns
ns
Notes
1
1
1
1
T
F ALL
Tfall_PD#
Fall/Rise time of PD# input
T
R ISE
Trise_PD#
1
U nless otherw ise noted, guaranteed by design and characterization, not 100% tested in production.
AC Electrical Characteristics–Low Power Differential Outputs
PARAMETER
SYMBOL
CONDITIONS
MIN
MAX
t
SLR
Differential Measurement
2.5
4
R ising Edge Slew Rate
t
F LR
Falling Edge Slew Rate
Differential Measurement
2.5
4
Single-ended Measurement
20
Slew Rate Variation
t
SLVAR
V
SWING
Differential Voltage Swing
Single-ended Measurement
Single-ended Measurement
300
550
Crossing Point Voltage
V
XABS
V
XABSVAR
Single-ended Measurement
140
Crossing Point Variation
V
HIGH
Maximum Output Voltage
Includes overshoot
1150
Includes undershoot
-300
Minimum Output Voltage
V
LOW
D
CYC
Duty Cycle
Differential Measurement
45
55
*TA = 0 - 70°C; Supply Voltage VD D = 3.3 V +/-5%, Rs=0ohm, CL=2pF
1
U nless otherw ise noted, guaranteed by design and characterization, not 100% tested in production.
2
Measurement taken for single ended waveform on a component test board (not in system)
3
Measurement taken from differential waveform on a component test board. (not in system)
4
Slew rate emastured through V_swing voltage range centered about differential zero
5
Vcross is defined at the voltage w here Clock = Clock#, measured on a component test board (not in system)
6
Only applies to the differential rising edge (Clock rising, Clock# falling)
7
UNITS
V/ns
V/ns
%
mV
mV
mV
mV
mV
%
N OTES
1,3,4
1,3,4
1,2,7
1,3
1,2,5,6
1,2,5,10
1,2,8
1,2,9
1,3
Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on
the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage
8
9
The max voltage including overshoot.
The min voltage including undershoot.
10
The total variation of all Vcross measurements in any particular system. Note this is a subset of V_cross min/mas (V_Cross
absolute) allowed. The intent is to limit Vcross induced modulation by setting C_cross_delta to be smaller than V_Cross absolute.
IDT®
LOW POWER PROGRAMMABLE TIMING CONTROL HUB
TM
FOR INTEL SYSTEMS
5
9LRS4206
REV A 012814
