DATASHEET
12-OUTPUT LOW POWER DIFFERENTIAL BUFFER FOR PCIE GEN3 AND QPI
9ZXL1230
General Description
The 9ZXL1230 is a small-footprint, low power 12-output
differential buffer that meets all the performance
requirements of the Intel DB1900Z specification. It is pin
compatible to the 9ZX21200. The 9ZXL1230 is backwards
compatible to PCIe Gen2 and QPI 6.4GT/s specifications. A
fixed, internal feedback path maintains low drift for critical
QPI applications.
Features/Benefits
•
Low-power push-pull outputs; Save power and board
•
•
•
•
•
space - no Rp
Pin compatible to 9ZX21200; easy path to >50% power
savings
Space-saving 56-pin QFN package
Fixed feedback path for 0ps input-to-output delay
9 Selectable SMBus Addresses; Mulitple devices can
share the same SMBus Segment
4 OE# pins; Hardware control of four outputs, other
outputs free run
PLL or bypass mode; PLL can dejitter incoming clock
and QPI applications
Recommended Application
12-output Low Power PCIe Gen3/QPI differential buffer for
Romley
Output Features
•
12 - 0.7V low-power HCSL-compatible output pairs
•
•
100MHz or 133MHz PLL mode operation; supports PCIe
•
Selectable PLL bandwidth; minimizes jitter peaking in
downstream PLL's
•
Spread Spectrum Compatible; tracks spreading input
clock for low EMI
Key Specifications
•
•
•
•
•
Cycle-to-cycle jitter <50ps
Output-to-output skew <65 ps
Input-to-output delay variation <50ps
PCIe Gen3 phase jitter <1.0ps RMS
QPI 9.6GT/s 12UI phase jitter <0.2ps RMS
Block Diagram
OE(8,6,4,2)#
DFB_OUT_NC
Z-PLL
(SS Compatible)
DIF(11:0)
DIF_IN
DIF_IN#
HIBW_BYPM_LOBW#
100M_133M#
CKPWRGD/PD#
SMB_A0_tri
SMB_A1_tri
SMBDAT
SMBCLK
Logic
IDT®
12-OUTPUT LOW POWER DIFFERENTIAL BUFFER FOR PCIE GEN3 AND QPI
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9ZXL1230
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9ZXL1230
12-OUTPUT LOW POWER DIFFERENTIAL BUFFER FOR PCIE GEN3 AND QPI
Pin Configuration
DIF_11#
DIF_10#
DIF_11
DIF_9#
DIF_8#
DIF_10
VDDIO
VDDIO
42
41
40
39
38
37
36
35
34
33
32
31
30
29
vOE2#
DIF_2#
DIF_3#
VDDIO
DIF_3
GND
DIF_7#
DIF_7
vOE6#
DIF_6#
DIF_6
GND
VDD
DIF_5#
DIF_5
vOE4#
DIF_4#
DIF_4
GND
vOE8#
VDDA
DIF_9
DIF_8
GND
GND
VDD
VDD
56 55 54 53 52 51 50 49 48 47 46 45 44 43
GNDA
NC
100M_133M#
HIBW_BYPM_LOBW#
CKPWRGD_PD#
GND
VDDR
DIF_IN
DIF_IN#
SMB_A0_tri
SMBDAT
SMBCLK
SMB_A1_tri
DFB_OUT_NC#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
DIF_0
DIF_0#
DIF_1#
DIF_1
DFB_OUT_NC
9ZXL1230
15 16 17 18 19 20 21 22 23 24 25 26 27 28
VDDIO
DIF_2
Note:
Pins with ^ prefix have internal 120K pullup
Pins with v prefix have internal 120K pulldowm
Power Management Table
PLL STATE
IF NOT IN
DIF(11:0)/
BYPASS
D IF(11:0)#
MODE
Low/Low
Low/Low
Running
OFF
ON
ON
CKPWR GD_PD#
0
1
DIF_IN/
D IF_IN#
X
Running
SMBus
EN bit
X
0
1
Functionality at Power-up (PLL mode)
100M_133M#
1
0
DIF_IN
MHz
100.00
133.33
DIF(11:0)
DIF_IN
DIF_IN
Power Connections
Pin Number
VDD
56
7
21,35,50
VDDIO
GND
1
6
20,29,36,42,
51
Description
Analog PLL
Analog Input
DIF clocks
22,28,43,49
IDT®
12-OUTPUT LOW POWER DIFFERENTIAL BUFFER FOR PCIE GEN3 AND QPI
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12-OUTPUT LOW POWER DIFFERENTIAL BUFFER FOR PCIE GEN3 AND QPI
PLL Operating Mode Readback Table
HiBW_BypM_LoBW#
Low (Low BW)
Mid (Bypass)
High (High BW)
Byte0, bit 7
0
0
1
Byte 0, bit 6
0
1
1
Tri-Level Input Thresholds
Level
Low
Mid
H igh
Voltage
<0.8V
1.2<Vin<1.8V
Vin > 2.2V
PLL Operating Mode
HiBW_BypM_LoBW#
MODE
Low
PLL Lo BW
Mid
Bypass
High
PLL Hi BW
NOTE: PLL is OFF in Bypass Mode
9ZXL1230 SMBus Addressing
Pin
SMB_A1_tri
0
0
0
M
M
M
1
1
1
SMB_A0_tri
0
M
1
0
M
1
0
M
1
SMBus Address
D8
DA
DE
C2
C4
C6
CA
CC
CE
IDT®
12-OUTPUT LOW POWER DIFFERENTIAL BUFFER FOR PCIE GEN3 AND QPI
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9ZXL1230
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9ZXL1230
12-OUTPUT LOW POWER DIFFERENTIAL BUFFER FOR PCIE GEN3 AND QPI
Pin Descriptions
PIN #
PIN NA ME
1 GNDA
2 NC
3
4
5
6
7
8
9
10
11
12
13
14
100M_133M#
HIBW_BYPM_LOBW#
CKPWRGD_PD#
GND
VDDR
DIF_IN
DIF_IN#
SMB_A0_tri
SMBDAT
SMBCLK
SMB_A1_tri
DFB_OUT_NC#
TYPE
DESCRIPTION
PWR Ground pin for the PLL core.
N/A N o Connection.
3.3V Input to select operating frequency
IN
See Functionality Table for Definition
Trilevel input to select High BW, Bypass or Low BW mode.
IN
See PLL Operating Mode Table for D etails.
N otifies device to sample latched inputs and start up on first high assertion, or exit Power Down Mode on
IN
subsequent assertions. Low enters Power Down Mode.
PWR Ground pin.
3.3V power for differential input clock (receiver). This VDD should be treated as an analog power rail and
PWR
filtered appropriately.
IN
0.7 V Differential TRUE input
IN
0.7 V Differential Complementary Input
SMBus address bit. This is a tri-level input that works in conjunction with the SMB_A1 to decode 1 of 9
IN
SMBus Addresses.
I/O D ata pin of SMBUS circuitry, 5V tolerant
IN
C lock pin of SMBU S circuitry, 5V tolerant
SMBus address bit. This is a tri-level input that works in conjunction with the SMB_A0 to decode 1 of 9
IN
SMBus Addresses.
C omplementary half of differential feedback output, provides feedback signal to the PLL for synchronization
OUT w ith input clock to eliminate phase error. This pin should NOT be connected on the circuit board, the feedback
is internal to the package.
True half of differential feedback output, provides feedback signal to the PLL for synchronization with the input
OUT clock to eliminate phase error. This pin should NOT be connected on the circuit board, the feedback is internal
to the package.
OUT 0.7V differential true clock output
OUT 0.7V differential Complementary clock output
OUT 0.7V differential true clock output
OUT 0.7V differential Complementary clock output
PWR Ground pin.
PWR Power supply, nominal 3.3V
PWR Power supply for differential outputs
OUT 0.7V differential true clock output
OUT 0.7V differential Complementary clock output
Active low input for enabling DIF pair 2.
IN
1 =disable outputs, 0 = enable outputs
OUT 0.7V differential true clock output
OUT 0.7V differential Complementary clock output
PWR Power supply for differential outputs
PWR Ground pin.
OUT 0.7V differential true clock output
OUT 0.7V differential Complementary clock output
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
DFB_OUT_NC
DIF_0
DIF_0#
DIF_1
DIF_1#
GND
VDD
VDDIO
DIF_2
DIF_2#
OE2#
DIF_3
DIF_3#
VDDIO
GND
DIF_4
DIF_4#
IDT®
12-OUTPUT LOW POWER DIFFERENTIAL BUFFER FOR PCIE GEN3 AND QPI
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9ZXL1230
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9ZXL1230
12-OUTPUT LOW POWER DIFFERENTIAL BUFFER FOR PCIE GEN3 AND QPI
Pin Descriptions (cont.)
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
OE4#
DIF_5
DIF_5#
VDD
GND
DIF_6
DIF_6#
OE6#
DIF_7
DIF_7#
GND
VDDIO
DIF_8
DIF_8#
OE8#
DIF_9
DIF_9#
VDDIO
VDD
GND
DIF_10
DIF_10#
DIF_11
DIF_11#
VDDA
IN
OUT
OUT
PWR
PWR
OUT
OUT
IN
OUT
OUT
PWR
PWR
OUT
OUT
IN
OUT
OUT
PWR
PWR
PWR
OUT
OUT
OUT
OUT
PWR
Active low input for enabling DIF pair 4
1 =disable outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential Complementary clock output
Power supply, nominal 3.3V
Ground pin.
0.7V differential true clock output
0.7V differential Complementary clock output
Active low input for enabling DIF pair 6.
1 =disable outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential Complementary clock output
Ground pin.
Power supply for differential outputs
0.7V differential true clock output
0.7V differential Complementary clock output
Active low input for enabling DIF pair 8.
1 =disable outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential Complementary clock output
Power supply for differential outputs
Power supply, nominal 3.3V
Ground pin.
0.7V differential true clock output
0.7V differential Complementary clock output
0.7V differential true clock output
0.7V differential Complementary clock output
3.3V power for the PLL core.
IDT®
12-OUTPUT LOW POWER DIFFERENTIAL BUFFER FOR PCIE GEN3 AND QPI
5
9ZXL1230
REV C 112015
