v4.0.1
ACT
™
2 Family FPGAs
Fe a t ur es
• Up to 8000 Gate Array Gates
(20,000 PLD equivalent gates)
• Replaces up to 200 TTL Packages
• Replaces up to eighty 20-Pin PAL
®
Packages
• Datapath Performance at 105 MHz
• 16-Bit Accumulator Performance to 39 MHz
• Two In-Circuit Diagnostic Probe Pins Support Speed
Analysis to 50 MHz
• Two High-Speed, Low-Skew Clock Networks
• I/O Drive to 10 mA
• Nonvolatile, User Programmable
• Logic Fully Tested Prior to Shipment
• 1.0-micron CMOS Technology
• Design Library with over 500 Macro Functions
• Single-Module Sequential Functions
• Wide-Input Combinatorial Functions
• Up to 1232 Programmable Logic Modules
• Up to 998 Flip-Flops
Pr od uc t F am i l y P r o f i l e
Device
Capacity
Gate Array Equivalent Gates
PLD Equivalent Gates
TTL Equivalent Packages
20-Pin PAL Equivalent Packages
Logic Modules
S-Modules
C-Modules
Flip-Flops (maximum)
Routing Resources
Horizontal Tracks/Channel
Vertical Tracks/Channel
PLICE Antifuse Elements
User I/Os (maximum)
Packages
1
A1225A
2,500
6,250
63
25
451
231
220
382
36
15
250,000
83
100 CPGA
100 PQFP
100 VQFP
84 PLCC
A1240A
4,000
10,000
100
40
684
348
336
568
36
15
400,000
104
132 CPGA
144 PQFP
176 TQFP
84 PLCC
A1280A
8,000
20,000
200
80
1,232
624
608
998
36
15
750,000
140
176 CPGA
160 PQFP
176 TQFP
84 PLCC
172 CQFP
85 MHz
67 MHz
36 MHz
Performance
2
16-Bit Prescaled Counters
16-Bit Loadable Counters
16-Bit Accumulators
105 MHz
70 MHz
39 MHz
100 MHz
69 MHz
38 MHz
Notes:
1. See the
“Product Plan” on page 3
for package availability.
2. Performance is based on ‘–2’ speed devices at commercial worst-case operating conditions using PREP Benchmarks, Suite #1, Version 1.2,
dated 3-28-93, any analysis is not endorsed by PREP.
D e ce m b e r 2 0 0 0
1
© 2000 Actel Corporation
A C T
™
2 F a m il y F P GA s
D es cr i p t i o n
The ACT™ 2 family represents Actel’s second generation of
field programmable gate arrays (FPGAs). The ACT 2 family
presents a two-module architecture, consisting of C-modules
and S-modules. These modules are optimized for both
combinatorial and sequential designs. Based on Actel’s
patented channeled array architecture, the ACT 2 family
provides significant enhancements to gate density and
performance while maintaining downward compatibility
with the ACT 1 design environment and upward
compatibility with the ACT 3 design environment. The
devices are implemented in silicon gate, 1.0-µm, two-level
metal CMOS, and employ Actel’s PLICE
®
antifuse
O r d e r i n g I nf o r m a t i o n
technology. This revolutionary architecture offers gate array
design flexibility, high performance, and fast
time-to-production with user programming. The ACT 2
family is supported by the Designer and Designer Advantage
Systems, which offers automatic pin assignment, validation
of electrical and design rules, automatic placement and
routing, timing analysis, user programming, and diagnostic
probe capabilities. The systems are supported on the
following platforms: 386/486™ PC, Sun
™
, and HP
™
workstations. The systems provide CAE interfaces to the
following design environments: Cadence, Viewlogic
®
,
Mentor Graphics
®
, and OrCAD™.
A1280
A
–
1
PG
176
C
Application (Temperature Range)
C = Commercial (0 to +70°C)
I = Industrial (–40 to +85°C)
M = Military (–55 to +125°C)
B = MIL-STD-883
Package Lead Count
Package Type
PL = Plastic J-Leaded Chip Carrier
PQ = Plastic Quad Flat Pack
CQ = Ceramic Quad Flat Pack
PG = Ceramic Pin Grid Array
TQ = Thin (1.4 mm) Quad Flat Pack
VQ = Very Thin (1.0 mm) Quad Flat Pack
Speed Grade
Blank = Standard Speed
–1 = Approximately 15% faster than Standard
–2 = Approximately 25% faster than Standard
Die Revision
A = 1.0-µm CMOS process
Part Number
A1225 = 2500 Gates
A1240 = 4000 Gates
A1280 = 8000 Gates
2
v4.0
A C T
™
2 F a m il y F PG A s
Pr od uc t P l a n
Speed Grade*
Std
A1225A Device
100-pin Ceramic Pin Grid Array (PG)
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
—
✔
—
✔
—
—
—
—
—
—
—
—
100-pin Plastic Quad Flat Pack (PQ)
✔
100-pin Very Thin (1.0 mm) Quad Flat Pack (VQ)
✔
84-pin Plastic Leaded Chip Carrier (PL)
A1240A Device
132-pin Ceramic Pin Grid Array (PG)
176-pin Thin (1.4 mm) Quad Flat Pack (TQ)
144-pin Plastic Quad Flat Pack (PQ)
84-pin Plastic Leaded Chip Carrier (PL)
A1280A Device
176-pin Ceramic Pin Grid Array (PG)
176-pin Thin (1.4 mm) Quad Flat Pack (TQ)
160-pin Plastic Quad Flat Pack (PQ)
172-pin Ceramic Quad Flat Pack (CQ)
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
—
—
✔
—
✔
—
—
✔
✔
—
—
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
—
—
✔
✔
✔
—
—
—
✔
—
—
—
✔
–1
–2
Application
C
I
M
B
Contact your Actel sales representatives for product availability.
Applications: C = Commercial
Availability:
✔
= Available
*Speed Grade:
I = Industrial
P = Planned
M = Military
— = Not Planned
B = MIL-STD-883
–1 = Approx. 15% faster than Standard
–2 = Approx. 25% faster than Standard
D ev i ce R es ou r c es
User I/Os
CPGA
Device
Series
A1225A
A1240A
A1280A
PQFP
PLCC
CQFP
TQFP
VQFP
Logic
Modules Gates 176-pin 132-pin 100-pin 160-pin 144-pin 100-pin 84-pin 172-pin 176-pin 100-pin
451
684
1232
2500
4000
8000
—
—
140
—
104
—
83
—
—
—
—
125
—
104
—
83
—
—
72
72
72
—
—
140
—
104
140
83
—
—
.
v4.0
3
A C T
™
2 F a m il y F P GA s
O pe r a t i ng C on d i t i on s
Abs ol ut e M axim u m Ra ti ngs
1
R ecom m en ded Oper at ing C ondi ti ons
Free air temperature range
Symbol
V
CC
V
I
V
O
I
IO
T
STG
Parameter
DC Supply Voltage
Input Voltage
Output Voltage
I/O Source/Sink
Current
2
Storage Temperature
Limits
–0.5 to +7.0
–0.5 to V
CC
+0.5
–0.5 to V
CC
+0.5
±20
–65 to +150
Units
V
V
V
mA
°C
Parameter
Temperature
Range
1
Power
Supply
Tolerance
Commercia Industria
l
l
0 to +70
–40 to
+85
±10
Military
–55 to
+125
±10
Units
°C
±5
%V
CC
Notes:
1. Stresses beyond those listed under “Absolute Maximum
Ratings” may cause permanent damage to the device.
Exposure to absolute maximum rated conditions for extended
periods may affect device reliability. Device should not be
operated outside the Recommended Operating Conditions.
2. Device inputs are normally high impedance and draw
extremely low current. However, when input voltage is greater
than V
CC
+ 0.5 V or less than GND – 0.5 V, the internal
protection diode will be forward biased and can draw excessive
current.
E lect r ica l Sp eci ficat i ons
Note:
1. Ambient temperature (T
A
) is used for commercial and
industrial; case temperature (T
C
) is used for military.
Commercial
Symbol
V
OH1
Parameter
(I
OH
= –10 mA)
2
(I
OH
= –6 mA)
(I
OH
= –4 mA)
V
OL1
V
IL
V
IH
Input Transition Time t
R
, t
F2
C
IO
I/O Capacitance
2, 3
Standby Current, I
CC4
(typical = 1 mA)
Leakage Current
5
–10
(I
OL
= 10 mA)
2
(I
OL
= 6 mA)
–0.3
2.0
0.5
0.33
0.8
V
CC
+ 0.3
500
10
2
10
Min.
2.4
3.84
Max.
Industrial
Min.
Max.
Military
Min.
Max.
Units
V
V
3.7
3.7
V
V
0.40
–0.3
2.0
0.8
V
CC
+ 0.3
500
10
10
–10
10
–10
–0.3
2.0
0.40
0.8
V
CC
+ 0.3
500
10
20
10
V
V
V
ns
pF
mA
µA
Notes:
1. Only one output tested at a time. V
CC
= min.
2. Not tested, for information only.
3. Includes worst-case 176 CPGA package capacitance. V
OUT
= 0 V, f = 1 MHz.
4. All outputs unloaded. All inputs = V
CC
or GND, typical I
CC
= 1 mA. I
CC
limit includes I
PP
and I
SV
during normal operation.
5. V
OUT
, V
IN
= V
CC
or GND.
4
v4.0
A C T
™
2 F a m il y F PG A s
Pa c ka ge T he r m a l C ha r a ct e r i s t i c s
Maximum junction temperature is 150°C.
A sample calculation of the absolute maximum power
dissipation allowed for a PQFP 160-pin package at
commercial temperature is as follows:
The device junction to case thermal characteristic is
θ
jc,
and the junction to ambient air characteristic is
θ
ja. The
thermal characteristics for
θ
ja are shown with two different
air flow rates.
Max. junction temp. (°C) – Max. commercial temp.
---------------------------------------------------------------------------------------------------------------------------- = 150°C – 70°C = 2.4 W
-
---------------------------------
θja
(°C/W)
33°C/W
θja
Still Air
35
30
23
25
48
40
38
37
43
32
θja
300 ft/min
17
15
12
15
40
32
30
28
35
25
Package Type
Ceramic Pin Grid Array
Pin Count
100
132
176
172
100
144
160
84
100
176
θjc
5
5
8
8
13
15
15
12
12
15
Units
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
°C/W
Ceramic Quad Flat Pack
Plastic Quad Flat Pack
1
Plastic Leaded Chip Carrier
2
Very Thin Quad Flat Pack
3
Thin Quad Flat Pack
4
Notes:(Maximum Power in Still Air)
1. Maximum Power Dissipation for PQFP packages are 1.9 Watts (100-pin), 2.3 Watts (144-pin), and 2.4 Watts (160-pin).
2. Maximum Power Dissipation for PLCC packages is 2.7 Watts.
3. Maximum Power Dissipation for VQFP packages is 2.3 Watts.
4. Maximum Power Dissipation for TQFP packages is 3.1 Watts.
Po w e r D i ss i pa t i o n
P = [I
CC
standby + I
CC
active] * V
CC
+ I
OL
* V
OL
* N +
I
OH
* (V
CC
– V
OH
) * M
Where:
I
CC
standby is the current flowing when no inputs or outputs
are changing.
I
CC
active is the current flowing due to CMOS switching.
I
OL
, I
OH
are TTL sink/source currents.
V
OL
, V
OH
are TTL level output voltages.
N equals the number of outputs driving TTL loads to V
OL
.
M equals the number of outputs driving TTL loads to V
OH
.
An accurate determination of N and M is problematical
because their values depend on the family type, design
details, and on the system I/O. The power can be divided
into two components: static and active.
S tat i c P ow er Co m ponen t
greater reduction in board-level power dissipation can be
achieved.
The power due to standby current is typically a small
component of the overall power. Standby power is
calculated below for commercial, worst case conditions.
I
CC
2 mA
V
CC
5.25V
Power
10.5 mW
The static power dissipated by TTL loads depends on the
number of outputs driving high or low and the DC load
current. Again, this value is typically small. For instance, a
32-bit bus sinking 4 mA at 0.33 V will generate 42 mW with
all outputs driving low, and 140 mW with all outputs driving
high. The actual dissipation will average somewhere
between as I/Os switch states with time.
Ac ti ve P ower Com po nent
Actel FPGAs have small static power components that
result in lower power dissipation than PALs or PLDs. By
integrating multiple PALs/PLDs into one FPGA, an even
Power dissipation in CMOS devices is usually dominated by
the active (dynamic) power dissipation. This component is
frequency dependent, a function of the logic and the
external I/O. Active power dissipation results from charging
internal chip capacitances of the interconnect,
unprogrammed antifuses, module inputs, and module
outputs, plus external capacitance due to PC board traces
v4.0
5
