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Accelerator Series FPGAs

– ACT

™

3 Family

Fe atur es

• Replaces up to twenty 32 macro-cell CPLDs

• Replaces up to one hundred 20-pin PAL

Packages

• Up to 1153 Dedicated Flip-Flops

• VQFP, TQFP, BGA, and PQFP Packages

• Nonvolatile, User Programmable

• Fully Tested Prior to Shipment

• 5.0V and 3.3V Versions

• Optimized for Logic Synthesis Methodologies

• Low-power CMOS Technology

A1415

1,500

3,750

200

104

264

100

—

100

—

108 MHz

63 MHz

110 MHz

250 MHz

7.5 ns

A1425

2,500

6,250

310

160

150

360

100

133

100, 160

—

100

—

132

108 MHz

63 MHz

110 MHz

250 MHz

7.5 ns

A1440

4,000

10,000

100

564

288

276

568

140

175

160

—

100

176

—

100 MHz

63 MHz

110 MHz

250 MHz

8.5 ns

A1460

6,000

15,000

150

848

432

416

768

168

207

—

160, 208

—

176

225

196

97 MHz

63 MHz

110 MHz

200 MHz

9.0 ns

A14100

10,000

25,000

250

100

1,377

697

680

1,153

228

257

—

208

—

313

256

93 MHz

63 MHz

105 MHz

200 MHz

9.5 ns

• Up to 10,000 Gate Array Equivalent Gates

(up to 25,000 equivalent PLD Gates)

• Highly Predictable Performance with 100% Automatic

Placement and Routing

• 7.5 ns Clock-to-Output Times

• Up to 250 MHz On-Chip Performance

• Up to 228 User-Programmable I/O Pins

• Four Fast, Low-Skew Clock Networks

• More than 500 Macro Functions

Device

Capacity

Gate Array Equivalent Gates

PLD Equivalent Gates

TTL Equivalent Packages (40 gates)

20-Pin PAL Equivalent Packages (100 gates)

Logic Modules

S-Module

C-Module

Dedicated Flip-Flops

User I/Os (maximum)

Packages

(by pin count)

CPGA

PLCC

PQFP

RQFP

VQFP

TQFP

BGA

CQFP

Performance

(maximum, worst-case commercial)

Chip-to-Chip

Accumulators (16-bit)

Loadable Counter (16-bit)

Prescaled Loadable Counters (16-bit)

Datapath, Shift Registers

Clock-to-Output (pad-to-pad)

Notes:

1. One flip-flop per S-Module, two flip-flops per I/O-Module.

2. See product plan on page 1-178 for package availability.

3. Based on A1415A-3, A1425A-3, A1440B-3, A1460B-3, and A14100B-3.

4. Clock-to-Output + Setup

S e p t e m b e r 19 9 7

1-175

De scrip tion

Actel’s ACT 3 Accelerator Series of FPGAs offers the

industry’s fastest high-capacity programmable logic device.

ACT 3 FPGAs offer a high perfomance, PCI compliant

programmable solution capable of 250 MHz on-chip

performance and 7.5 nanosecond clock-to-output, with

capacities spanning from 1,500 to 10,000 gate array

equivalent gates. For further information regarding PCI

compliance of ACT 3 devices, see “Accelerator Series

FPGAs—ACT 3 PCI Compliant Family.”

The ACT 3 family builds on the proven two-module

architecture consisting of combinatorial and sequential logic

modules used in Actel’s 3200DX and 1200XL families. In

addition, the ACT 3 I/O modules contain registers which

deliver 7.5 nanosecond clock-to-out times. The devices

contain four clock distribution networks, including dedicated

array and I/O clocks, supporting very fast synchronous and

asynchronous designs. In addition, routed clocks can be used

to drive high fanout signals such as flip-flop resets and output

enables.

The ACT 3 family is supported by Actel’s Designer Series

Development System which offers automatic placement and

routing (with automatic or fixed pin assignments), static

timing anlaysis, user programming, and debug and diagnostic

probe capabilities. The Designer Series is supported on the

following platforms: 486/Pentium class PC’s, Sun

‚ and HP

‚

workstations. The software provides CAE interfaces to

Cadence, Mentor Graphics

, OrCAD

™

and Viewlogic

‚

design environments. Additional platforms are supported

through Actel’s Industry Alliance Program, including DATA

I/O (ABEL FPGA) and MINC.

Predictable Performance* (Worst-Case Commercial)

Accumulators (16-bit)

63 MHz

110 MHz

250 MHz

Loadable Counters (16-bit)

Prescaled Loadable Counters (16-bit)

Shift Registers

S yste m Pe rfo rmance M odel

Chip #1

I/O Module

Chip #2

I/O Module

35 pF

I/O CLK

CKHS

TRACE

INSU

Chip-to-Chip Performance

(Worst-Case Commercial)

CKHS

A1425A-3

A1460A-3

7.5

9.0

TRACE

1.0

INSU

1.8

1.3

Total

10.3 ns

11.3 ns

MHz

1-176

Ac celera tor S eries FPGA s – A C T

™

3 Fami ly

Order ing Informati on

A14100

–

208

Application (Temperature Range)

C = Commercial (0 to +70°C)

I = Industrial (–40 to +85°C)

M = Military (–55 to +125°C)

B = MIL-STD-883

Package Lead Count

Package Type

PG = Ceramic Pin Grid Array

PL = Plastic Leaded Chip Carrier

PQ = Plastic Quad Flatpack

RQ = Plastic Power Quad Flatpack

VQ = Very Thin (1.0 mm) Quad Flatpack

TQ = Thin (1.4 mm) Quad Flatpack

CQ = Ceramic Quad Flatpack

BG = Plastic Ball Grid Array

Speed Grade

Std = Standard Speed

–1 = Approximately 15% faster than Standard

–2 = Approximately 25% faster than Standard

–3 = Approximately 35% faster than Standard

Die Revision

Part Number

A1415A =

A14V15A =

A1425A =

A14V25A =

A1440A =

A14V40A =

A1460A =

A14V60A =

A14100A =

A14V100A =

1500 Gates

1500 Gates (3.3V)

2500 Gates

2500 Gates (3.3V)

4000 Gates

4000 Gates (3.3V)

6000 Gates

6000 Gates (3.3V)

10000 Gates

10000 Gates (3.3V)

1-177

P ro du c t Pla n

Speed Grade*

Std

A1415A Device

84-pin Plastic Leaded Chip Carrier (PLCC)

100-pin Plastic Quad Flatpack (PQFP)

100-pin Very Thin Quad Flatpack (VQFP)

100-pin Ceramic Pin Grid Array (CPGA)

A14V15A Device

84-pin Plastic Leaded Chip Carrier (PLCC)

100-pin Very Thin Quad Flatpack (VQFP)

A1425A Device

84-pin Plastic Leaded Chip Carrier (PLCC)

100-pin Plastic Quad Flatpack (PQFP)

100-pin Very Thin Quad Flatpack (VQFP)

132-pin Ceramic Quad Flatpack (CQFP)

133-pin Ceramic Pin Grid Array (CPGA)

160-pin Plastic Quad Flatpack (PQFP)

A14V25A Device

84-pin Plastic Leaded Chip Carrier (PLCC)

100-pin Very Thin Quad Flatpack (VQFP)

160-pin Plastic Quad Flatpack (PQFP)

A1440A Device

84-pin Plastic Leaded Chip Carrier (PLCC)

100-pin Very Thin Quad Flatpack (VQFP)

160-pin Plastic Quad Flatpack (PQFP)

175-pin Ceramic Pin Grid Array (CPGA)

176-pin Thin Quad Flatpack (TQFP)

A14V40A Device

84-pin Plastic Leaded Chip Carrier (PLCC)

100-pin Very Thin Quad Flatpack (VQFP)

160-pin Plastic Quad Flatpack (PQFP)

176-pin Thin Quad Flatpack (TQFP)

A1460A Device

160-pin Plastic Quad Flatpack (PQFP)

176-pin Thin Quad Flatpack (TQFP)

196-pin Ceramic Quad Flatpack (CQFP)

207-pin Ceramic Pin Grid Array (CPGA)

208-pin Plastic Quad Flatpack (PQFP)

225-pin Platic Ball Grid Array (BGA)

Applications:

†

= Commercial

= Industrial

= Military

= MIL-STD-883

Commercial Only

Availability:

= Available

P = Planned

— = Not Planned

—

P†

—

†

—

†

—

–1

–2

–3

Application

—

†

* Speed Grade: –1 = Approx. 15% faster than Standard

–2 = Approx. 25% faster than Standard

–3 = Approx. 35 % faster than Standard.

1-178

Ac celera tor S eries FPGA s – A C T

™

3 Fami ly

Produc t Plan

(continued)

Speed Grade*

Std

A14V60A Device

160-pin Plastic Quad Flatpack (PQFP)

176-pin Thin Quad Flatpack (TQFP)

208-pin Plastic Quad Flatpack (PQFP)

A14100A Device

208-pin Power Quad Flatpack (RQFP)

257-pin Ceramic Pin Grid Array (CPGA)

313-pin Plastic Ball Grid Array (BGA)

256-pin Ceramic Quad Flatpack (CQFP)

A14V100A Device

208-pin Power Quad Flatpack (RQFP)

313-pin Plastic Ball Grid Array (BGA)

Applications:

†

= Commercial

= Industrial

= Military

= MIL-STD-883

Commercial Only

Availability:

—

= Available

P = Planned

— = Not Planned

—

†

—

†

—

–1

–2

–3

Application

* Speed Grade: –1 = Approx. 15% faster than Standard

–2 = Approx. 25% faster than Standard

–3 = Approx. 35 % faster than Standard.

P lastic Device R es ources

User I/Os

PLCC

Device

Series

A1415

A1425

A1440

A1460

A14100

Logic

Modules

200

310

564

848

1377

Gates

1500

2500

4000

6000

10000

84-pin

—

100-pin

—

PQFP, RQFP

160-pin

—

100

131

—

208-pin

—

167

175

VQFP

100-pin

—

TQFP

176-pin

—

140

151

—

BGA

225-pin

—

168

—

313-pin

—

228

1-179