A29L320A Series
4M X 8 Bit / 2M X 16 Bit CMOS 3.0 Volt-only,
Boot Sector Flash Memory
Document Title
4M X 8 Bit / 2M X 16 Bit CMOS 3.0 Volt-only, Boot Sector Flash Memory
Revision History
Rev. No.
0.0
0.1
0.2
1.0
1.1
History
Initial issue
Error correction: Top/Bottom device ID code and pin configurations
Change Table1 & Program/Erasure time
Final version release
Modify symbol “L” outline dimensions in TSOP 48L package
Issue Date
April 12, 2006
May 25, 2006
July 3, 2006
January 5, 2007
November 15, 2007
Remark
Preliminary
Final
(November, 2007, Version 1.1)
AMIC Technology, Corp.
A29L320A Series
4M X 8 Bit / 2M X 16 Bit CMOS 3.0 Volt-only,
Boot Sector Flash Memory
Features
Single power supply operation
- Regulated voltage range: 2.7 to 3.6 volt read and write
operations for compatibility with high performance 3 volt
microprocessors
Access times:
- 70/80/90/120 (max.)
Current:
-
2mA active read current at 1MHz
-
10mA active read current at 5MHz
- 20 mA typical program/erase current
-
500 nA typical CMOS standby or Automatic Sleep Mode
current
Flexible sector architecture
-
Eight 8 Kbyte sectors
-
Sixty-three 64 kbyte sectors
-
Any combination of sectors can be erased
-
Supports full chip erase
-
Sector protection:
Unlock Bypass Program Command
- Reduces overall programming time when issuing
multiple program command sequence
Top or bottom boot block configurations available
Embedded Algorithms
- Embedded Erase algorithm will automatically erase the
entire chip or any combination of designated sectors and
verify the erased sectors
- Embedded Program algorithm automatically writes and
verifies data at specified addresses
Typical 100,000 program/erase cycles per sector
20-year data retention at 125°C
-
Reliable operation for the life of the system
CFI (Common Flash Interface) compliant
- Provides device-specific information to the system,
allowing host software to easily reconfigure for different
Flash devices
Compatible with JEDEC-standards
- Pinout and software compatible with single-power-supply
Flash memory standard
-
Superior inadvertent write protection
Data
Polling and toggle bits
-
Provides a software method of detecting completion of
program or erase operations
Ready /
BUSY
pin (RY /
BY
)
- Provides a hardware method of detecting completion of
program or erase operations
Erase Suspend/Erase Resume
-
Suspends a sector erase operation to read data from, or
program data to, a non-erasing sector, then resumes the
erase operation
Hardware reset pin (
RESET
)
-
Hardware method to reset the device to reading array
data
WP
/ACC input pin
-
Write protect (
WP
) function allows protection of two
outermost boot sectors, regardless of sector protect
status
-
Acceleration (ACC) function provides accelerated
program times
Hardware/Software temporary sector block unprotect
command allows code changes in previously locked
sectors
Hardware/Software sector protect/unprotect command
Package options
-
48-pin TSOP (I) or 48-ball TFBGA
-
All Pb-free (Lead-free) products are RoHS compliant
General Description
The A29L320A is a 32Mbit, 3.3 volt-only Flash memory
organized as 2,097,152 words of 16 bits or 4,194,304 bytes
of 8 bits each. The 8 bits of data appear on I/O
0
- I/O
7
; the 16
bits of data appear on I/O
0
~I/O
15
. The A29L320A is offered in
48-ball TFBGA and 48-Pin TSOP packages. This device is
designed to be programmed in-system with the standard
system 3.3 volt VCC supply. Additional 12.0 volt VPP is not
required for in-system write or erase operations. However,
the A29L320A can also be programmed in standard EPROM
programmers.
The A29L320A has the first toggle bit, I/O
6
, which indicates
whether an Embedded Program or Erase is in progress, or it
is in the Erase Suspend. Besides the I/O
6
toggle bit, the
A29L320A has a second toggle bit, I/O
2
, to indicate whether
the addressed sector is being selected for erase. The
A29L320A also offers the ability to program in the Erase
Suspend mode. The standard A29L320A offers access times
of 70,80,90 and 120ns, allowing high-speed microprocessors
to operate without wait states. To eliminate bus contention
the device has separate chip enable (
CE
), write enable
(
WE
) and output enable (
OE
) controls.
The device requires only a single 3.3 volt power supply for
both read and write functions. Internally generated and
regulated voltages are provided for the program and erase
operations.
The A29L320A is entirely software command set compatible
with the JEDEC single-power-supply Flash standard.
Commands are written to the command register using
standard microprocessor write timings. Register contents
serve as input to an internal state-machine that controls the
erase and programming circuitry. Write cycles also internally
latch addresses and data needed for the programming and
(November, 2007, Version 1.1)
1
AMIC Technology, Corp.
A29L320A Series
erase operations. Reading data out of the device is similar to
reading from other Flash or EPROM devices.
Device programming occurs by writing the proper program
command sequence. This initiates the Embedded Program
algorithm - an internal algorithm that automatically times the
program pulse widths and verifies proper program margin.
Device erasure occurs by executing the proper erase
command sequence. This initiates the Embedded Erase
algorithm - an internal algorithm that automatically
preprograms the array (if it is not already programmed)
before executing the erase operation. During erase, the
device automatically times the erase pulse widths and
verifies proper erase margin. The Unlock Bypass mode
facilitates faster programming times by requiring only two
write cycles to program data instead of four.
The host system can detect whether a program or erase
operation is complete by observing the RY /
BY
pin, or by
reading the I/O
7
(
Data
Polling) and I/O
6
(toggle) status bits.
After a program or erase cycle has been completed, the
device is ready to read array data or accept another
command.
The sector erase architecture allows memory sectors to be
erased and reprogrammed without affecting the data
contents of other sectors. The A29L320A is fully erased
when shipped from the factory.
The hardware sector protection feature disables operations
for both program and erase in any combination of the
sectors of memory. This can be achieved via programming
equipment.
The Erase Suspend/Erase Resume feature enables the user
to put erase on hold for any period of time to read data from,
or program data to, any other sector that is not selected for
erasure. True background erase can thus be achieved.
The hardware
RESET
pin terminates any operation in
progress and resets the internal state machine to reading
array data. The
RESET
pin may be tied to the system reset
circuitry. A system reset would thus also reset the device,
enabling the system microprocessor to read the boot-up
firmware from the Flash memory.
The device offers two power-saving features. When
addresses have been stable for a specified amount of time,
the device enters the automatic sleep mode. The system can
also place the device into the standby mode. Power
consumption is greatly reduced in both these modes.
Pin Configurations
TSOP (I)
A15
A14
A13
A12
A11
A10
A9
A8
A19
A20
WE
RESET
NC
WP/ACC
RY/BY
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A16
BYTE
VSS
I/O
15
(A-1)
I/O
7
I/O
14
I/O
6
I/O
13
I/O
5
I/O
12
I/O
4
VCC
I/O
11
I/O
3
I/O
10
I/O
2
I/O
9
I/O
1
I/O
8
I/O
0
OE
VSS
CE
A0
A29L320AV
(November, 2007, Version 1.1)
2
AMIC Technology, Corp.
A29L320A Series
Pin Configurations (continued)
TFBGA
TFBGA
Top View, Balls Facing Down
A6
B6
C6
D6
E6
F6
G6
H6
A13
A5
A12
B5
A14
C5
A15
D5
A16
E5
BYTE
F5
I/O
15
(A-1)
G5
VSS
H5
A9
A4
A8
B4
A10
C4
A11
D4
I/O
7
E4
I/O
14
F4
I/O
13
G4
I/O
6
H4
WE
A3
RESET
B3
NC
C3
A19
D3
I/O
5
E3
I/O
12
F3
VCC
G3
I/O
4
H3
RY/BY
A2
WP/ACC
B2
A18
C2
A20
D2
I/O
2
E2
I/O
10
F2
I/O
11
G2
I/O
3
H2
A7
A1
A17
B1
A6
C1
A5
D1
I/O
0
E1
I/O
8
F1
I/O
9
G1
I/O
1
H1
A3
A4
A2
A1
A0
CE
OE
VSS
(November, 2007, Version 1.1)
3
AMIC Technology, Corp.
A29L320A Series
Block Diagram
RY/BY
VCC
VSS
Sector Switches
Erase Voltage
Generator
State
Control
PGM Voltage
Generator
Chip Enable
Output Enable
Logic
STB
I/O
0
- I/O
15
(A-1)
RESET
Input/Output
Buffers
WE
BYTE
WP/ACC
Command
Register
CE
OE
Data Latch
STB
VCC Detector
Timer
Address Latch
Y-Decoder
Y-Gating
A0-A20
X-decoder
Cell Matrix
Pin Descriptions
Pin No.
A0 – A20
I/O
0
- I/O
14
I/O
15
I/O
15
(A-1)
A-1
Address Inputs
Data Inputs/Outputs
Data Input/Output, Word Mode
LSB Address Input, Byte Mode
Chip Enable
Write Enable
Output Enable
Hardware Reset
Selects Byte Mode or Word Mode
Ready/
BUSY
- Output
Ground
Power Supply
Pin not connected internally
Hardware Write Protect / Acceleration Pin
Description
CE
WE
OE
RESET
BYTE
RY/
BY
VSS
VCC
NC
WP
/ACC
(November, 2007, Version 1.1)
4
AMIC Technology, Corp.
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