Revision 13
SmartFusion Customizable System-on-Chip (cSoC)
Microcontroller Subsystem (MSS)
•
Hard 100 MHz 32-bit ARM
®
Cortex
®
-M3 Processor
– 1.25 DMIPS/MHz Throughput from Zero Wait State
Memory
– Memory Protection Unit (MPU)
– Single Cycle Multiplication, Hardware Divide
– JTAG Debug (4 wires), Serial Wire Debug (SWD, 2
wires), and Single Wire Viewer (SWV) Interfaces
Internal Memory
– Embedded Nonvolatile Flash Memory (eNVM), 128
Kbytes to 512 Kbytes
– Embedded High-Speed SRAM (eSRAM), 16 Kbytes
to 64 Kbytes, Implemented in 2 Physical Blocks to
Enable Simultaneous Access from 2 Different
Masters
Multi-Layer AHB Communications Matrix
– Provides up to 16 Gbps of On-Chip Memory
Bandwidth,
1
Allowing Multi-Master Schemes
10/100 Ethernet MAC with RMII Interface
2
Programmable External Memory Controller, Which
Supports:
– Asynchronous Memories
– NOR Flash, SRAM, PSRAM
– Synchronous SRAMs
Two I
2
C Peripherals
Two 16550 Compatible UARTs
Two SPI Peripherals
Two 32-bit Timers
32-bit Watchdog Timer
8-channel DMA Controller to Offload the Cortex-M3 from
Data Transactions
Clock Sources
– 32 KHz to 20 MHz Main Oscillator
– Battery-Backed 32 KHz Low Power Oscillator with
Real-Time Counter (RTC)
– 100 MHz Embedded RC Oscillator; 1% Accurate
– Embedded Analog PLL with 4 Output Phases (0, 90,
180, 270)
Based on proven ProASIC
®
3 FPGA Fabric
Low Power, Firm-Error Immune 130-nm, 7-Layer Metal,
Flash-Based CMOS Process
Nonvolatile, Instant On, Retains Program When
Powered Off
350 MHz System Performance
Embedded SRAMs and FIFOs
– Variable Aspect Ratio 4,608-Bit SRAM Blocks
– x1, x2, x4, x9, and x18 Organizations
– True Dual-Port SRAM (excluding x18)
•
•
•
– Programmable Embedded FIFO Control Logic
Secure ISP with 128-bit AES via JTAG
FlashLock
®
to Secure FPGA Contents
Five Clock Conditioning Circuits (CCCs) with up to 2
Integrated Analog PLLs
– Phase Shift, Multiply/Divide, and Delay Capabilities
– Frequency: Input 1.5–350 MHz, Output 0.75 to
350 MHz
•
Programmable Analog
Analog Front-End (AFE)
•
Up to Three 12-Bit SAR ADCs
– 500 Ksps in 12-Bit Mode
– 550 Ksps in 10-Bit Mode
– 600 Ksps in 8-Bit Mode
Internal 2.56 V Reference or Optional External
Reference
One First-Order
DAC (sigma-delta) per ADC
– 8-Bit, 16-Bit, or 24-Bit 500 Ksps Update Rate
Up to 5 High-Performance Analog Signal Conditioning
Blocks (SCB) per Device, Each Including:
– Two High-Voltage Bipolar Voltage Monitors (with 4
input ranges from ±2.5 V to –11.5/+14 V) with 1%
Accuracy
– High Gain Current Monitor, Differential Gain = 50, up
to 14 V Common Mode
– Temperature Monitor (Resolution = ¼°C in 12-Bit
Mode; Accurate from –55°C to 150°C)
Up to Ten High-Speed Voltage Comparators
(t
pd
= 15 ns)
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Analog Compute Engine (ACE)
•
•
•
•
High-Performance FPGA
•
•
•
•
•
Offloads Cortex-M3–Based MSS from Analog
Initialization and Processing of ADC, DAC, and SCBs
Sample Sequence Engine for ADC and DAC Parameter
Set-Up
Post-Processing Engine for Functions such as Low-
Pass Filtering and Linear Transformation
Easily Configured via GUI in Libero
®
System-on-Chip
(SoC) Software
FPGA I/Os
– LVDS, PCI, PCI-X, up to 24 mA IOH/IOL
– Up to 350 MHz
MSS I/Os
– Schmitt Trigger, up to 6 mA IOH, 8 mA IOL
– Up to 180 MHz
Single 3.3 V Power Supply with On-Chip 1.5 V Regulator
External 1.5 V Is Allowed by Bypassing Regulator
(digital VCC = 1.5 V for FPGA and MSS, analog VCC =
3.3 V and 1.5 V)
I/Os and Operating Voltage
•
•
•
•
1 Theoretical maximum
2 A2F200 and larger devices
March 2015
© 2015 Microsemi Corporation
I
SmartFusion Customizable System-on-Chip (cSoC)
SmartFusion cSoC Family Product Table
A2F060
FPGA Fabric
System Gates
Tiles (D-flip-flops)
RAM Blocks (4,608 bits)
Microcontroller Subsystem (MSS)
Flash (Kbytes)
SRAM (Kbytes)
Cortex-M3 processor with MPU
10/100 Ethernet MAC
External Memory Controller (EMC)
DMA
I
2
C
SPI
16550 UART
32-Bit Timer
PLL
32 KHz Low Power Oscillator
100 MHz On-Chip RC Oscillator
Main Oscillator (32 KHz to 20 MHz)
Programmable Analog
ADCs (8-/10-/12-bit SAR)
DACs (8-/16-/24-bit sigma-delta)
Signal Conditioning Blocks (SCBs)
Comparator*
Current Monitors*
Temperature Monitors*
Bipolar High Voltage Monitors*
1
2
2
1
1
1
1
A2F060
1
1
1
2
1
1
2
–
60,000
1,536
8
A2F060
128
16
Yes
No
26-/16-bit
address/data
8 Ch
2
2
1
2
2
1
1
1
1
A2F200
2
2
4
8
4
4
8
1
2
1
1
1
A2F500
2
2
4
8
4
4
8
3
3
5
10
5
5
10
A2F200
200,000
4,608
8
A2F200
256
64
Yes
Yes
26-bit address,16-bit data
8 Ch
2
2
1
2
2
1
2
–
A2F500
500,000
11,520
24
A2F500
512
64
Yes
Yes
26-/16-bit address/data
8 Ch
2
2
TQ144 CS288 FG256 PQ208 CS288 FG256 FG484 PQ208 CS288 FG256 FG484
TQ144 CS288 FG256 PQ208 CS288 FG256 FG484 PQ208 CS288 FG256 FG484
TQ144 CS288 FG256 PQ208 CS288 FG256 FG484 PQ208 CS288 FG256 FG484
Note:
*These functions share I/O pins and may not all be available at the same time. See the "Analog Front-End Overview" section in
the
http://www.microsemi.com/index.php?option=com_docman&task=doc_download&gid=130925
for details.
II
R evis i o n 13
SmartFusion Customizable System-on-Chip (cSoC)
Package I/Os: MSS + FPGA I/Os
Device
Package
Direct Analog Inputs
Shared Analog Inputs
Total Analog Inputs
Analog Outputs
MSS I/Os
3,4
FPGA I/Os
Total I/Os
TQ144
11
4
15
1
21
5
33
6
70
A2F060
1
CS288
11
4
15
1
28
5
68
112
FG256
11
4
15
1
26
5
66
108
PQ208
8
16
24
1
22
66
113
A2F200
2
CS288
8
16
24
2
31
78
135
FG256
8
16
24
2
25
66
117
FG484
8
16
24
2
41
94
161
PQ208
8
16
24
1
22
66
6
113
A2F500
2
CS288
8
16
24
2
31
78
135
FG256
8
16
24
2
25
66
117
FG484
12
20
32
3
41
128
204
Notes:
1. There are no LVTTL capable direct inputs available on A2F060 devices.
2. These pins are shared between direct analog inputs to the ADCs and voltage/current/temperature monitors.
3. 16 MSS I/Os are multiplexed and can be used as FPGA I/Os, if not needed for MSS. These I/Os support Schmitt triggers and
support only LVTTL and LVCMOS (1.5 / 1.8 / 2.5, 3.3 V) standards.
4. 9 MSS I/Os are primarily for 10/100 Ethernet MAC and are also multiplexed and can be used as FPGA I/Os if Ethernet MAC is
not used in a design. These I/Os support Schmitt triggers and support only LVTTL and LVCMOS (1.5 / 1.8 / 2.5, 3.3 V
standards.
5. 10/100 Ethernet MAC is not available on A2F060.
6. EMC is not available on the A2F500 PQ208 and A2F060 TQ144 package.
Table 1 • SmartFusion cSoC Package Sizes Dimensions
Package
Length × Width (mm\mm)
Nominal Area (mm
2
)
Pitch (mm)
Height (mm)
TQ144
20 × 20
400
0.5
1.40
PQ208
28 × 28
784
0.5
3.40
CS288
11 × 11
121
0.5
1.05
FG256
17 × 17
289
1.0
1.60
FG484
23 × 23
529
1.0
2.23
SmartFusion cSoC Device Status
Device
A2F060
A2F200
A2F500
Status
Preliminary: CS288, FG256, TQ144
Production: CS288, FG256, FG484, PQ208
Production: CS288, FG256, FG484, PQ208
Revision 13
III
SmartFusion Customizable System-on-Chip (cSoC)
SmartFusion cSoC Block Diagram
Supervisor
PLL
OSC
RC
Cortex-M3
+
JTAG
NVIC
SysTick
PPB
SysReg
ENVM
WDT
32 KHz
RTC
3V
SWD
MPU
ESRAM
Microcontroller Subsystem
Programmable Analog
FPGA Fabric
–
S
D
I
SPI 1
APB
APB
SPI 2
AHB Bus Matrix
UART 1
EFROM
Timer1
UART 2
I2C 1
IAP
PDMA
APB
EMC
10/100
EMAC
Timer2
I2C 2
SCB
Temp.
Mon.
Volt Mon.
(ABPS)
Analog Compute
Engine
Curr.
Mon.
Comparator
ADC
Sample Sequencing
Engine
DAC
(SDD)
VersaTiles
............
............
SCB
Temp.
Mon.
Volt Mon.
(ABPS)
....
........
ADC
Post Processing
Engine
DAC
(SDD)
Curr.
Mon.
Comparator
SRAM
SRAM
SRAM
........
SRAM
SRAM
SRAM
Legend:
SDD – Sigma-delta DAC
SCB – Signal conditioning block
PDMA – Peripheral DMA
IAP – In-application programming
ABPS – Active bipolar prescaler
WDT – Watchdog Timer
SWD – Serial Wire Debug
IV
R evis i o n 13
SmartFusion Customizable System-on-Chip (cSoC)
SmartFusion cSoC System Architecture
Bank 0
Bank 1
Bank 5
ISP AES Decryption
Embedded FlashROM
(eFROM)
Charge Pumps
Embedded NVM
(eNVM)
Bank 4
Cortex-M3 Microcontroller Subsystem (MSS)
Embedded SRAM
(eSRAM)
Bank 2
SCB
SCB
ADC and DAC
ADC and DAC
SCB
SCB
Bank 3
Osc.
CCC
PLL/CCC
MSS
FPGA
Analog
Note:
Architecture for A2F200
Revision 13
V
