v6.1
40MX and 42MX FPGA Families
Features
High Capacity
•
•
•
•
•
Single-Chip ASIC Alternative
3,000 to 54,000 System Gates
Up to 2.5 kbits Configurable Dual-Port SRAM
Fast Wide-Decode Circuitry
Up to 202 User-Programmable I/O Pins
HiRel Features
•
•
•
•
Commercial, Industrial, Automotive, and Military
Temperature Plastic Packages
Commercial, Military Temperature, and MIL-STD-883
Ceramic Packages
QML Certification
Ceramic Devices Available to DSCC SMD
Ease of Integration
•
•
•
•
•
•
Mixed-Voltage Operation (5.0V or 3.3V for core and
I/Os), with PCI-Compliant I/Os
Up to 100% Resource Utilization and 100% Pin
Locking
Deterministic, User-Controllable Timing
Unique In-System Diagnostic and Verification
Capability with Silicon Explorer II
Low Power Consumption
IEEE Standard 1149.1 (JTAG) Boundary Scan Testing
High Performance
•
•
•
•
•
5.6 ns Clock-to-Out
250 MHz Performance
5 ns Dual-Port SRAM Access
100 MHz FIFOs
7.5 ns 35-Bit Address Decode
Product Profile
Device
Capacity
System Gates
SRAM Bits
Logic Modules
Sequential
Combinatorial
Decode
Clock-to-Out
SRAM Modules
(64x4 or 32x8)
Dedicated Flip-Flops
Maximum Flip-Flops
Clocks
User I/O (maximum)
PCI
Boundary Scan Test (BST)
Packages (by pin count)
PLCC
PQFP
VQFP
TQFP
CQFP
PBGA
A40MX02
3,000
–
–
295
–
9.5 ns
–
–
147
1
57
–
–
44, 68
100
80
–
–
–
A40MX04
6,000
–
–
547
–
9.5 ns
–
–
273
1
69
–
–
44, 68, 84
100
80
–
–
–
A42MX09
14,000
–
348
336
–
5.6 ns
–
348
516
2
104
–
–
84
100, 160
100
176
–
–
A42MX16
24,000
–
624
608
–
6.1 ns
–
624
928
2
140
–
–
84
100, 160, 208
100
176
–
–
A42MX24
36,000
–
954
912
24
6.1 ns
–
954
1,410
2
176
Yes
Yes
84
160, 208
–
176
–
–
A42MX36
54,000
2,560
1,230
1,184
24
6.3 ns
10
1,230
1,822
6
202
Yes
Yes
–
208, 240
–
–
208, 256
272
April 2009
© 2009 Actel Corporation
i
See the Actel website for the latest version of the datasheet.
40MX and 42MX FPGA Families
Ordering Information
A42MX16 _
1
PQ
100
ES
Application (Temperature Range)
Blank = Commercial (0 to +70˚C)
I
= Industrial (–40 to +85˚C)
M
= Military (–55 to +125˚C)
B
= MIL-STD-883
A
= Automotive (–40 to +125˚C)
Package Lead Count
Package Type
PL =
Plastic Leaded Chip Carrier
PQ =
Plastic Quad Flat Pack
TQ =
Thin (1.4 mm) Quad Flat Pack
VQ =
Very Thin (1.0 mm) Quad Flat Pack
BG =
Plastic Ball Grid Array
CQ =
Ceramic Quad Flat Pack
Speed Grade
Blank = Standard Speed
–1 =
Approximately 15% Faster than Standard
–2 =
Approximately 25% Faster than Standard
–3 =
Approximately 35% Faster than Standard
–F =
Approximately 40% Slower than Standard
Part Number
A40MX02
=
3,000 System Gates
A40MX04
=
6,000 System Gates
A42MX09
=
14,000 System Gates
A42MX16
=
24,000 System Gates
A42MX24
=
36,000 System Gates
A42MX36
=
54,000 System Gates
Plastic Device Resources
User I/Os
Device
A40MX02
A40MX04
A42MX09
A42MX16
A42MX24
A42MX36
PLCC
44-Pin
34
34
–
–
–
–
PLCC
68-Pin
57
57
–
–
–
–
PLCC
84-Pin
–
69
72
72
72
–
PQFP
PQFP
PQFP
PQFP
100-Pin 160-Pin 208-Pin 240-Pin
57
69
83
83
–
–
–
–
101
125
125
–
–
–
–
140
176
176
–
–
–
–
–
202
VQFP
80-Pin
57
69
–
–
–
–
VQFP
TQFP
PBGA
100-Pin 176-Pin 272-Pin
–
–
83
83
–
–
–
–
104
140
150
–
–
–
–
–
–
202
Note: Package Definitions
PLCC = Plastic Leaded Chip Carrier, PQFP = Plastic Quad Flat Pack, TQFP = Thin Quad Flat Pack, VQFP = Very Thin Quad Flat Pack,
PBGA = Plastic Ball Grid Array
ii
v6.1
40MX and 42MX FPGA Families
Ceramic Device Resources
User I/Os
Device
A42MX36
Note: Package Definitions
CQFP 208-Pin
176
CQFP 256-Pin
202
CQFP = Ceramic Quad Flat Pack
Temperature Grade Offerings
Package
PLCC 44
PLCC 68
PLCC 84
PQFP 100
PQFP 160
PQFP 208
PQFP 240
VQFP 80
VQFP 100
TQFP 176
PBGA 272
CQFP 208
CQFP 256
Note:
C = Commercial
I = Industrial
A = Automotive
M = Military
B = MIL-STD-883 Class B
C, I, A, M
C, I, A, M
C, I, A, M
C, I, A, M
C, I, A, M
C, I, A, M
C, I, A, M
C, I, M
C, M, B
C, M, B
C, I, A, M
A40MX02
C, I, M
C, I, A, M
A40MX04
C, I, M
C, I, M
C, I, A, M
C, I, A, M
C, I, A, M
C, I, A, M
C, I, A, M
C, I, M
C, I, M
C, I, M
C, I, A, M
C, I, A, M
C, I, A, M
C, I, A, M
C, I, A, M
C, I, M
A42MX09
A42MX16
A42MX24
A42MX36
Speed Grade Offerings
–F
C
I
A
M
B
✓
Std
✓
✓
✓
✓
✓
✓
✓
–1
✓
✓
–2
✓
✓
–3
✓
✓
Note:
Refer to the
40MX and 42MX Automotive Family FPGAs
datasheet for details on automotive-grade MX offerings.
Contact your local Actel representative for device availability.
v6.1
iii
40MX and 42MX FPGA Families
Table of Contents
40MX and 42MX FPGA Families
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
MX Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
Other Architectural Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8
Development Tool Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13
Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13
5.0V Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14
5V TTL Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15
3.3V Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16
3.3V LVTTL Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17
Mixed 5.0V/3.3V Operating Conditions (for 42MX Devices Only) . . . . . . . . . . . . . 1-18
Mixed 5.0V/3.3V Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18
Output Drive Characteristics for 5.0V PCI Signaling . . . . . . . . . . . . . . . . . . . . . . . . 1-19
Output Drive Characteristics for 3.3V PCI Signaling . . . . . . . . . . . . . . . . . . . . . . . . 1-20
Junction Temperature (T
J
) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-22
Package Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-22
Timing Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-23
Parameter Measurement
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-25
Sequential Module Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-26
Sequential Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-27
Decode Module Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-28
SRAM Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-28
Dual-Port SRAM Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-28
Predictable Performance: Tight Delay Distributions . . . . . . . . . . . . . . . . . . . . . . . 1-30
Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-30
Temperature and Voltage Derating Factors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-31
PCI System Timing Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-35
PCI Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-35
Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-36
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-77
Package Pin Assignments
44-Pin PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
68-Pin PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
84-Pin PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
v 6 .1
v
