A49LF004
4 Mbit CMOS 3.3Volt-only Firmware Hub Flash Memory
Preliminary
Document Title
4 Mbit CMOS 3.3 Volt-only Firmware Hub Flash Memory
Revision History
Rev. No.
0.0
History
Initial issue
Issue Date
November 21, 2003
Remark
Preliminary
PRELIMINARY
(November, 2003, Version 0.0)
AMIC Technology, Corp.
A49LF004
4 Mbit CMOS 3.3Volt-only Firmware Hub Flash Memory
Preliminary
FEATURES
• Single Power Supply Operation
-
Low voltage range: 3.0 V - 3.6 V for Read and Write
Operations
• Standard Intel Firmware Hub Interface
-
Read compatible to Intel® 82802 Firmware
Hub devices
• Memory Configuration
-
512K x 8 (4 Mbit)
• Block Architecture
-
4Mbit: eight uniform 64KByte blocks
-
Supports full chip erase for Address/Address
Multiplexed (A/A Mux) mode
•
Automatic Erase and Program Operation
-
Embedded Byte Program and Block/Chip Erase
algorithms
-
Typical 10 µs/byte programming time
-
Typical 1s block erase time
• Two Operational Modes
-
Firmware Hub Interface (FWH) Mode for in-system
operation
-
Address/Address Multiplexed (A/A Mux) Interface
Mode for programming equipment
• Firmware Hub (FWH) Mode
-
33 MHz synchronous operation with PCI bus
-
5-signal communication interface for in-system read
and write operations
-
-
-
-
-
-
-
Standard SDP Command Set
Data# Polling (I/O
7
) and Toggle Bit (I/O
6
) features
Block Locking Register for all blocks
4 ID pins for multi-chip selection
5 GPI pins for General Purpose Input Register
TBL# pin for hardware write protection to Boot Block
WP# pin for hardware write protection to whole
memory array except Boot Block
• Address/Address Multiplexed (A/A Mux) Mode
-
11-pin multiplexed address and 8-pin data I/O
interface
-
Supports fast programming on EPROM programmers
-
Standard SDP Command Set
-
Data# Polling (I/O
7
) and Toggle Bit (I/O
6
) features
• Lower Power Consumption
-
Typical 12mA active read current
-
Typical 24mA program/erase current
•
High Product Endurance
-
Guarantee 100,000 program/erase cycles for each
block
-
Minimum 20 years data retention
• Compatible Pin-out and Packaging
-
32-pin (8 mm x 14 mm) TSOP (TYPE I)
-
32-pin PLCC
GENERAL DESCRIPTION
The A49LF004 flash memory device is designed to be read-
compatible with the Intel 82802 Firmware Hub (FWH)
device for PC-BIOS application. This device is designed to
use a single low voltage, range from 3.0 Volt to 3.6 Volt
power supply to perform in-system or off-system read and
write operations. It provides protection for the storage and
update of code and data in addition to adding system
design flexibility through five general-purpose inputs. Two
interface modes are supported by the A49LF004: Firmware
Hub (FWH) Interface mode for In-System programming and
Address/Address Multiplexed (A/A Mux) mode for fast
factory programming of PC-BIOS applications.
The memory is divided into eight uniform 64Kbyte blocks
that can be erased independently without affecting the data
in other blocks. Blocks also can be protected individually to
prevent accidental Program or Erase commands from
modifying the memory. The Program and Erase operations
are executed by issuing the Program/Erase commands into
the command interface by which activating the internal
control logic to automatically process the Program/Erase
procedures. The device can be programmed on a byte-by-
byte basis after performing the Erase operation. In addition
to the Block Erase operation, the Chip Erase feature is
provided in A/A Mux mode that allows the whole memory to
be erased in one single Erase operation. The A49LF004
provides the status detection such as Data# Polling and
Toggle Bit Functions in both FWH and A/A Mux modes. The
process or completion of Program and Erase operations
can be detected by reading the status bits.
The A49LF004 is offered in 32-lead TSOP and 32-lead
PLCC packages. See Figures 1 and 2 for pin assignments
and Table 1 for pin descriptions.
PRELIMINARY
(November, 2003, Version 0.0)
1
AMIC Technology, Corp.
A49LF004
PIN CONFIGURATIONS
RST# (RST#)
A9 (FGPI3)
4
3
2
1
32
31
A7 (FGPI1)
A6 (FGPI0)
A5 (WP#)
A4 (TBL#)
A3 (ID3)
A2 (ID2)
A1 (ID1)
A0 (ID0)
I/O
0
(FWH0)
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
30
A10 (FGPI4)
R/C# (CLK)
VDD (VDD)
A8 (FGPI2)
NC
29
28
27
IC (IC)
VSS (VSS)
NC
NC
VDD (VDD)
OE# (INIT#)
WE# (FWH4)
RB# (RES)
I/O
7
(RES)
32-lead PLCC
Top View
26
25
24
23
22
21
I/O
1
(FWH1)
I/O
2
(FWH2)
I/O
3
(FWH3)
VSS (VSS)
I/O
4
(RES)
I/O
5
(RES)
(*) Designates FWH Mode
FIGURE 1: Pin Assignments for 32-Lead PLCC
I/O
6
(RES)
NC
NC
NC
VSS (VSS)
IC (IC)
A10 (FGPI4)
R/C# (CLK)
VDD (VDD)
NC
RST# (RST#)
A9 (FGPI3)
A8 (FGPI2)
A7 (FGPI1)
A6 (FGPI0)
A5 (WP#)
A4 (TBL#)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
(*) Designates FWH Mode
32-lead TSOP (8
MM
X 14
MM
)
Top View
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE# (INIT#)
WE# (FWH4)
VDD (VDD)
I/O
7
(RES)
I/O
6
(RES)
I/O
5
(RES)
I/O
4
(RES)
I/O
3
(FWH3)
VSS (VSS)
I/O
2
(FWH2)
I/O
1
(FWH1)
I/O
0
(FWH0)
A0 (ID0)
A1 (ID1)
A2 (ID2)
A3 (ID3)
FIGURE 2: Pin Assignments for 32-Lead TSOP
PRELIMINARY
(November, 2003, Version 0.0)
2
AMIC Technology, Corp.
A49LF004
BLOCK DIAGRAM
FWH[3:0]
CLK
FWH4
ID[3:0]
FGPI[4:0]
A[10:0]
I/O
7
~ I/O
0
WE#
OE#
R/C#
IC
RST#
RB#
Y-Decoder
Address Latch
FWH Mode
Interface
Control Logic
Input/Output
Buffers
A/A Mux
Mode
Interface
High Voltage
Generator
Data Latch
Y-Gating
X-decoder
Cell Matrix
PRELIMINARY
(November, 2003, Version 0.0)
3
AMIC Technology, Corp.
A49LF004
Table 1: Pin Description
Interface
Symbol
Pin Name
Type
A/A
Mux
X
X
X
X
FWH
Descriptions
Inputs for addresses during Read and Write operations in A/A
Mux mode. Row and column addresses are latched by R/C# pin.
To output data during Read cycle and receive input data during
Write cycle in A/A Mux mode. The outputs are in tri-state when
OE# is high.
To control the data output buffers.
To control the Write operations.
To determine which interface is operational. When held high, A/A
Mux mode is enabled and when held low, FWH mode is enabled.
This pin must be setup at power-up or before return from reset
and not change during device operation. This pin is internally
pulled down with a resistor between 20-100 KΩ.
This is the second reset pin for in-system use. INIT# and RST#
pins are internally combined and initialize a device reset when
driven low.
These four pins are part of the mechanism that allows multiple
FWH devices to be attached to the same bus. To identify the
component, the correct strapping of these pins must be set. The
boot device must have ID[3:0]=0000 and it is recommended that
all subsequent devices should use sequential up-count
strapping. These pins are internally pulled down with a resistor
between 20-100 KΩ.
These individual inputs can be used for additional board
flexibility. The state of these pins can be read immediately at
boot, through FWH internal registers. These inputs should be at
their desired state before the start of the PCI clock cycle during
which the read is attempted, and should remain in place until the
end of the Read cycle. Unused FGPI pins must not be floated.
To prevent any write operations to the Boot Block when driven
low, regardless of the state of the block lock registers. When
TBL# is high it disables hardware write protection for the top
Boot Block. This pin cannot be left unconnected.
I/O Communications in FWH mode.
To provide a clock input to the device. This pin is the same as
that for the PCI clock and adheres to the PCI specifications.
Input communication in FWH mode.
To reset the operation of the device
When low, prevents any write operations to all but the highest
addressable block. When WP# is high it disables hardware write
protection for these blocks. This pin cannot be left unconnected.
This pin determines whether the address pins are pointing to the
row addresses or the column addresses in A/A Mux mode.
To determine if the device is busy in write operations. Valid only
in A/A Mux mode.
X
PWR
PWR
X
X
X
X
X
X
Reserved. These pins must be left unconnected.
To provide power supply (3.0-3.6Volt).
Circuit ground. All VSS pins must be grounded.
Unconnected pins.
A
10
-A
0
I/O
7
-I/O
0
OE#
WE#
Address
Data
Output Enable
Write Enable
Interface
Configuration Pin
IN
I/O
IN
IN
IC
IN
X
X
INIT#
Initialize
IN
X
ID[3:0]
Identification Inputs
IN
X
FGPI[4:0]
General Purpose
Inputs
IN
X
TBL#
FWH[3:0]
CLK
FWH4
RST#
WP#
R/C#
RB#
RES
VDD
VSS
NC
Top Block Lock
FWH I/Os
Clock
FWH Input
Reset
Write Protect
Row/Column Select
Ready/Busy#
Reserved
Power Supply
Ground
No Connection
IN
I/O
IN
IN
IN
IN
IN
OUT
X
X
X
X
X
X
X
X
X
1. IN=Input, OUT=output, I/O=Input/Output, PWR=Power
PRELIMINARY
(November, 2003, Version 0.0)
4
AMIC Technology, Corp.
嵌入式系统
