Discontinued – v3.0
ProASIC
®
500K Family
F ea t u re s an d B e n e fi t s
H ig h C a p ac it y
I/O
• 100,000 to 475,000 System Gates
• 14k to 63k Bits of Two-Port SRAM
• 106 to 440 User I/Os
P e r f o r m an c e
• Mixed 2.5V/3.3V Support with Individually-Selectable
Voltage and Slew Rate
• 3.3V, PCI Compliance (PCI Revision 2.2)
S e c ur e P r o gr a m m in g
The Industry’s Most Effective Security Key Prevents Read
Back of Programming Bit Stream
S t a n da r d F P G A a nd A S I C D es ig n F lo w
• 33 MHz PCI 32-bit PCI
• Internal System Performance up to 250 MHz
• External System Performance up to 100 MHz
Lo w P ow e r
• Low Impedance Flash Switches
• Segmented Hierarchical Routing Structure
• Small, Efficient Logic Cells
H ig h P e r f o r m a nc e R o u t in g H ie r ar ch y
• Flexibility with Choice of Industry-Standard Front-End
Tools
• Efficient Design Through Front-End Timing and Gate
Optimization
I S P S u pp o r t
• In-System Programming (ISP) with Silicon Sculptor and
Flash Pro
S R A M s a nd F I F O s
•
•
•
•
Ultra Fast Local Network
Efficient Long Line Network
High Speed Very Long Line Network
High Performance Global Network
• Up to 150 MHz Synchronous and Asynchronous Operation
• Netlist Generator Ensures Optimal Usage of Embedded
Memory Blocks
B o u nd a r y S c an T e st
No nv o la t ile a n d Re pro g r am m a bl e Fl as h
T e c hn o log y
IEEE Std. 1149.1 (JTAG) Compliant
• Live at Power Up
• No Configuration Device Required
• Retains Programmed Design During Power-Down/
Power-Up Cycles
P ro A S I C P r o du c t P ro fi l e
Device
Maximum System Gates
Typical Gates
Maximum Flip-Flops
Embedded RAM Bits
Embedded RAM Blocks (256 X 9)
Logic Tiles
Global Routing Resources
Maximum User I/Os
JTAG
PCI
Package
(by Pin Count)
PQFP
PBGA
FBGA
A500K050
100,000
43,000
5,376
14k
6
5,376
4
204
Yes
Yes
208
272
144
A500K130
290,000
105,000
12,800
45k
20
12,800
4
306
Yes
Yes
208
272, 456
144, 256
A500K180
370,000
150,000
18,432
54k
24
18,432
4
362
Yes
Yes
208
456
256
A500K270
475,000
215,000
26,880
63k
28
26,880
4
440
Yes
Yes
208
456
256, 676
February 2002
1
© 2002 Actel Corporation
Pr oAS IC
®
5 0 0 K F a m i l y
G e n e ra l D e s cr i p t i o n
The ProASIC 500K family’s nonvolatile Flash technology
combines the advantages of ASICs with the benefits of
programmable devices. ProASIC 500K devices shorten
time-to-production by enabling designers to create
high-density systems using existing ASIC or FPGA design
flows and tools. ASIC migration is not necessary for any
volume because the family offers cost effective
reprogrammable solutions, ideal for applications in the
networking, telecom, computer, and consumer markets.
The ProASIC 500K family consists of four devices ranging
from 100k to 475k system gates and with up to 63k bits of
O r d er i n g In f or m a t i o n
A500K130
PQ
208
embedded two-port memory. These memory blocks include
hardwired FIFO circuitry as well as circuits to generate or
check parity. This minimizes external logic gate count and
complexity while maximizing flexibility and utility.
P r o c es s T ec h no lo g y
The ProASIC 500K family achieves its nonvolatile and
reprogrammability through an advanced 0.25μ, four-level
metal LVCMOS process enhanced with Flash technology.
The use of standard CMOS design techniques to implement
logic and control functions results in highly predictable
performance and gate array compatibility.
Application (Ambient Temperature Range)
Blank = Commercial (0 to +70˚ C)
I = Industrial (-40 to +85˚ C)
PP = Pre-production
ES = Engineering Silicon (Room Temperature Only)
Package Lead Count
Package Type
BG = Plastic Ball Grid Array
PQ = Plastic Quad Flat Pack
FG = Fine Ball Grid Array
Part Number
A500K050 =
A500K130 =
A500K180 =
A500K270 =
100,000 Equivalent System Gates
290,000 Equivalent System Gates
370,000 Equivalent System Gates
475,000 Equivalent System Gates
Note:
This family has been discontinued.
2
Discontinued – v3.0
Pr oAS IC
®
5 0 0 K F a m i l y
P ro d u ct P l a n
Application
C
A500K050 Device
144-Pin Fine Ball Grid Array (FBGA)
208-Pin Plastic Quad Flat Pack (PQFP)
272-Pin Plastic Ball Grid Array (PBGA)
A500K130 Device
144-Pin Fine Ball Grid Array (FBGA)
208-Pin Plastic Quad Flat Pack (PQFP)
272-Pin Plastic Ball Grid Array (PBGA)
256-Pin Plastic Ball Grid Array (PBGA)
456-Pin Plastic Ball Grid Array (PBGA)
A500K180 Device
208-Pin Plastic Quad Flat Pack (PQFP)
256-Pin Plastic Ball Grid Array (PBGA)
456-Pin Plastic Ball Grid Array (PBGA)
A500K270 Device
208-Pin Plastic Quad Flat Pack (PQFP)
256-Pin Plastic Ball Grid Array (PBGA)
456-Pin Plastic Ball Grid Array (PBGA)
676-Pin Fine Ball Grid Array (FBGA)
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
I
Contact your Actel sales representative for package availability.
Applications: C = Commercial
Availability:
✔
= Available – Contact your Actel Sale’s representative for the latest
I = Industrial
availability information.
P l a s t i c D e v i c e R e s ou r c es
User I/Os
Device
A500K050
A500K130
A500K180
A500K270
PQFP
208-Pin
164
164
164
164
PBGA
272-Pin
204
204
—
—
PBGA
456-Pin
—
306
362
362
FBGA
144-Pin
106
106
—
—
FBGA
256-Pin
—
192
192
192
FBGA
676-Pin
—
—
—
440
Package Definitions
PQFP = Plastic Quad Flat Pack, PBGA = Plastic Ball Grid Array, FBGA = Fine Ball Grid Array
Discontinued – v3.0
3
Pr oAS IC
®
5 0 0 K F a m i l y
P ro A S I C 5 0 0 K A r c h i te c tu r e
The ProASIC 500K family’s proprietary architecture
provides granularity comparable to gate arrays. Unlike
SRAM-based FPGAs that utilize look-up tables or
architectural mapping during design, ProASIC device
designs are directly synthesized to gates. That streamlines
the design flow, increases design productivity, and
eliminates dependencies on vendor-specific design tools.
The ProASIC 500K device core
consists of a
™
Sea-of-Tiles (Figure
1),
each of which can be configured as
a 3-input logic function (e.g., NAND gate, D-Flip-Flop, etc.)
by programming the appropriate Flash switch
interconnections (See
Figure 2 on page 5
and
Figure 3 on
page 5).
Gates and larger functions are connected with four
levels of routing hierarchy. Flash memory bits are
distributed throughout the device to provide nonvolatile,
reconfigurable interconnect programming. Flash switches
are programmed to connect signal lines to the appropriate
logic cell inputs and outputs. Dedicated high-performance
lines are connected as needed for fast, low-skew global
signal distribution throughout the core. Maximum core
utilization is possible for virtually any design.
The ProASIC 500K devices also contain embedded two-port
SRAM blocks with built-in FIFO/RAM control logic.
Programming options include synchronous or asynchronous
operation, two-port RAM configurations, user defined depth
and width, and parity generation or checking. Table 3 on
page 12 lists the 24 basic memory configurations.
F la sh S w it c h
In the ProASIC Flash switch, two transistors share the
floating gate which stores the programming information.
One is the Flash transistor which stores programming
information and in which erasing is performed. The second
transistor connects/separates routing elements or
configuration signal lines (Figure
2 on page 5).
L og ic T ile
The logic tile cell,
Figure 3 on page 5,
has three inputs (any
or all of which can be inverted) and one output (which can
connect to both ultra fast local and efficient long line
routing resources). Any three-input one-output logic
function, except a three input XOR, can be configured as
one tile. Two multiplexers with feedback paths through the
NAND gates allow the tile to be configured as a latch with
clear or set, or as a flip-flop with clear or set. Thus, the tiles
can flexibly map logic and sequential gates of a design.
256x9 Two-Port SRAM
or FIFO Block
Logic Tile
Figure 1 •
The ProASIC Device Architecture
4
Discontinued – v3.0
Pr oAS IC
®
5 0 0 K F a m i l y
Sel 1
Sel 2
Floating Gate
Switch In
Word
Switch Out
Figure 2 •
Flash Switch
Local Routing
In 1
Efficient Long
Line Routing
In 2 (CLK)
In 3 (Reset)
Figure 3 •
Core Logic Tile
Ro ut in g Re so u r ce s
The routing structure of the ProASIC 500K devices is
designed to provide high performance through a flexible
four-level hierarchy of routing resources: ultra fast local
resources, efficient long line resources, high speed very long
line resources, and high performance global networks.
The ultra fast local resources are dedicated lines that allow
the output of each tile to connect directly to every input of
the eight surrounding tiles (Figure
4 on page 6).
The efficient long line resources provide routing for longer
distances and higher fanout connections. These resources
vary in length (spanning 1, 2, or 4 tiles), run both vertically
and horizontally, and cover the entire ProASIC device
(Figure
5 on page 6).
Each tile can drive signals onto the
efficient long line resources, while the resources can also
access every input of any tile. The routing software
automatically inserts active buffers to limit loading effects
due to distance and fanout.
The high speed very long line resources, spanning across
the entire device with minimal delay, are used to route very
long or very high fanout nets. These resources run vertically
and horizontally, providing multiple access to each group of
tiles throughout the device (Figure
6 on page 7).
The high performance global networks’ clock trees are low
skew, high fanout nets that are accessible from four
dedicated pins or from internal logic (Figure
7 on page 8).
These nets are typically used to distribute clocks, resets,
and other high fanout nets requiring a minimum skew. The
global networks are implemented as clock trees, and signals
can be introduced at any junction. These can be employed
hierarchically, with signals accessing every input on all
tiles.
C l oc k R e s ou r c es
ProASIC’s high-drive routing structure provides four global
networks, each accessible from either a dedicated global
pad or a logic tile. Global lines provide optimized worst-case
clock skew of 0.3ns.
Discontinued – v3.0
5
