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A54SX16A-2BG208M

FPGA, 1452 CLBS, 24000 GATES, 167 MHz, PQFP208
现场可编程门阵列, 1452 CLBS, 24000 门, 167 MHz, PQFP208

器件类别:半导体    可编程逻辑器件   

厂商名称:ETC1

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器件参数
参数名称
属性值
功能数量
1
端子数量
208
最大工作温度
70 Cel
最小工作温度
0.0 Cel
最大供电/工作电压
2.75 V
最小供电/工作电压
2.25 V
额定供电电压
2.5 V
加工封装描述
塑料, 方型扁平式封装-208
状态
TRANSFERRED
工艺
CMOS
包装形状
SQUARE
包装尺寸
FLATPACK, FINE PITCH
表面贴装
Yes
端子形式
GULL WING
端子间距
0.5000 mm
端子涂层
锡 铅
端子位置
包装材料
塑料/环氧树脂
温度等级
COMMERCIAL
组织
1452 CLBS, 24000 门
最大FCLK时钟频率
167 MHz
可配置逻辑模块数量
1452
可编程逻辑类型
FIELD PROGRAMMABLE GATE 阵列
等效门电路数量
24000
一个CLB模块最大延时
1.9 ns
文档预览
v5.1
SX-A Family FPGAs
Leading-Edge Performance
250 MHz System Performance
350 MHz Internal Performance
Specifications
12,000 to 108,000 Available System Gates
Up to 360 User-Programmable I/O Pins
Up to 2,012 Dedicated Flip-Flops
0.22
µ
/ 0.25
µ
CMOS Process Technology
Features
Hot-Swap Compliant I/Os
Power-Up/Down Friendly (No Sequencing Required
for Supply Voltages)
66 MHz PCI Compliant
Nonvolatile, Single-Chip Solution
Configurable I/O Support for 3.3 V / 5 V PCI, 5 V
TTL, 3.3 V LVTTL, 2.5 V LVCMOS2
2.5 V, 3.3 V, and 5 V Mixed-Voltage Operation with
5 V Input Tolerance and 5 V Drive Strength
Devices Support Multiple Temperature Grades
Configurable Weak-Resistor Pull-Up or Pull-Down
for I/O at Power-Up
Individual Output Slew Rate Control
Up to 100% Resource Utilization and 100% Pin
Locking
Deterministic, User-Controllable Timing
Unique In-System Diagnostic and Verification
Capability with Silicon Explorer II
Boundary-Scan Testing in Compliance with IEEE
Standard 1149.1 (JTAG)
Actel Secure Programming Technology with
FuseLock™ Prevents Reverse Engineering and
Design Theft
Table 1 •
SX-A Product Profile
Device
Capacity
Typical Gates
System Gates
Logic Modules
Combinatorial Cells
Dedicated Flip-Flops
Maximum Flip-Flops
Maximum User I/Os
Global Clocks
Quadrant Clocks
Boundary Scan Testing
3.3 V / 5 V PCI
Input Set-Up (External)
Speed Grades
Temperature Grades
Package (by pin count)
PQFP
TQFP
PBGA
FBGA
CQFP
A54SX08A
8,000
12,000
768
512
256
512*
130
3
0
Yes
Yes
0 ns
–F, Std, –1, –2
C, I, A, M
208
100, 144
144
A54SX16A
16,000
24,000
1,452
924
528
990
180
3
0
Yes
Yes
0 ns
–F, Std, –1, –2, –3
C, I, A, M
208
100, 144
144, 256
A54SX32A
32,000
48,000
2,880
1,800
1,080
1,980
249
3
0
Yes
Yes
0 ns
–F, Std, –1, –2, –3
C, I, A, M
208
100, 144, 176
329
144, 256, 484
208, 256
A54SX72A
72,000
108,000
6,036
4,024
2,012
4,024
360
3
4
Yes
Yes
0 ns
–F, Std, –1, –2, –3
C, I, A, M
208
256, 484
208, 256
Note:
*A maximum of 512 registers is possible if all 512 C cells are used to build an additional 256 registers
February 2005
© 2005 Actel Corporation
i
See the Actel website for the latest version of the datasheet.
SX-A Family FPGAs
Ordering Information
A54SX16A
2
PQ
208
Application (Temperature Range)
Blank = Commercial (0 to +70˚)
I = Industrial (-40 to +85˚C)
A = Automotive (-40 to +125˚C)
M = Military (-55 to +125˚C)
B = MIL-STD-883 Class B
Package Lead Count
Package Type
BG = 1.27 mm Plastic Ball Grid Array
FG = 1.0 mm Fine Pitch Ball Grid Array
PQ = Plastic Quad Flat Pack
TQ = Thin (1.4 mm) Quad Flat Pack
CQ = Ceramic Quad Flat Pack*
Speed Grade
Blank = Standard Speed
–1 = Approximately 15% Faster than Standard
–2 = Approximately 25% Faster than Standard
–3 = Approximately 35% Faster than Standard
–F = Approximately 40% Slower than Standard
Part Number
A54SX08A = 12,000 System Gates
A54SX16A = 24,000 System Gates
A54SX32A = 48,000 System Gates
A54SX72A = 108,000 System Gates
Note:
*For more information about the CQFP package options, refer to the
HiRel SX-A datasheet.
Device Resources
User I/Os (Including Clock Buffers)
Device
A54SX08A
A54SX16A
A54SX32A
A54SX72A
208-Pin
PQFP
130
175
174
171
100-Pin
TQFP
81
81
81
144-Pin
TQFP
113
113
113
176-Pin
TQFP
147
329-Pin
PBGA
249
144-Pin
FBGA
111
111
111
256-Pin
FBGA
180
203
203
484-Pin
FBGA
249
360
Notes:
Package Definitions: PQFP = Plastic Quad Flat Pack, TQFP = Thin Quad Flat Pack, PBGA = Plastic Ball Grid Array,
FBGA = Fine Pitch Ball Grid Array
ii
v5.1
SX-A Family FPGAs
Temperature Grade Offering
Package
PQ208
TQ100
TQ144
TQ176
BG329
FG144
FG256
FG484
CQ208
CQ256
Notes:
1.
2.
3.
4.
5.
6.
7.
C = Commercial
I = Industrial
A = Automotive
M = Military
B = Mil-Std-883 Class B
For more information regarding automotive products, refer to the
SX-A Automotive Family FPGAs
datasheet.
For more information regarding Mil-Temp and ceramic packages, refer to the
HiRel SX-A Family FPGAs
datasheet.
C,I,A,M
C,I,A,M
C,I,A,M
A54SX08A
C,I,A,M
C,I,A,M
C,I,A,M
A54SX16A
C,I,A,M
C,I,A,M
C,I,A,M
A54SX32A
C,I,A,M
C,I,A,M
C,I,A,M
C,I,M
C,I,M
C,I,A,M
C,I,A,M
C,I,M
C,M,B
C,M,B
C,I,A,M
C,I,A,M
C,M,B
C,M,B
A54SX72A
C,I,A,M
Speed Grade and Temperature Grade Matrix
F
Commercial
Industrial
Automotive
Military
Mil-Std. 883B
Notes:
1. For more information regarding automotive products, refer to the
SX-A Automotive Family FPGAs
datasheet.
2. For more information regarding Mil-Temp and ceramic packages, refer to the
HiRel SX-A Family FPGAs
datasheet.
Std
–1
–2
–3
Contact your Actel Sales representative for more information on availability.
v5.1
iii
SX-A Family FPGAs
Table of Contents
General Description
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
SX-A Family Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
Other Architectural Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13
Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14
Detailed Specifications
Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Typical SX-A Standby Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
PCI Compliance for the SX-A Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11
SX-A Timing Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
Sample Path Calculations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
Output Buffer Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
AC Test Loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
Input Buffer Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
C-Cell Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
Cell Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
Temperature and Voltage Derating Factors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18
Package Pin Assignments
208-Pin PQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
100-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5
144-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8
176-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11
329-Pin PBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14
144-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18
256-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-21
484-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26
iv
v5.1
SX-A Family FPGAs
Table of Contents
Datasheet Information
List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
International Traffic in Arms Regulations (ITAR) and Export Administration
Regulations (EAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
v5.1
v
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器件捷径:
00 01 02 03 04 05 06 07 08 09 0A 0C 0F 0J 0L 0M 0R 0S 0T 0Z 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 1H 1K 1M 1N 1P 1S 1T 1V 1X 1Z 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 2G 2K 2M 2N 2P 2Q 2R 2S 2T 2W 2Z 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 3G 3H 3J 3K 3L 3M 3N 3P 3R 3S 3T 3V 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4M 4N 4P 4S 4T 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5E 5G 5H 5K 5M 5N 5P 5S 5T 5V 60 61 62 63 64 65 66 67 68 69 6A 6C 6E 6F 6M 6N 6P 6R 6S 6T 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7M 7N 7P 7Q 7V 7W 7X 80 81 82 83 84 85 86 87 88 89 8A 8D 8E 8L 8N 8P 8S 8T 8W 8Y 8Z 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9F 9G 9H 9L 9S 9T 9W
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