v3.2
SX Family FPGAs
u e
™
Leading Edge Performance
•
•
•
•
320 MHz Internal Performance
3.7 ns Clock-to-Out (Pin-to-Pin)
0.1 ns Input Setup
0.25 ns Clock Skew
Features
•
•
•
•
•
•
•
•
•
•
66 MHz PCI
CPLD and FPGA Integration
Single-Chip Solution
100% Resource Utilization with 100% Pin Locking
3.3 V and 5.0 V Operation with 5.0 V Input Tolerance
Very Low Power Consumption
Deterministic, User-Controllable Timing
Unique In-System Diagnostic and Debug Capability
with Silicon Explorer II
Boundary Scan Testing in Compliance with IEEE
Standard 1149.1 (JTAG)
Secure Programming Technology Prevents Reverse
Engineering and Design Theft
Specifications
•
•
•
•
12,000 to 48,000 System Gates
Up to 249 User-Programmable I/O Pins
Up to 1,080 Flip-Flops
0.35 µ CMOS
SX Product Profile
Device
Capacity
Typical Gates
System Gates
Logic Modules
Combinatorial Cells
Register Cells (Dedicated Flip-Flops)
Maximum User I/Os
Clocks
JTAG
PCI
Clock-to-Out
Input Setup (external)
Speed Grades
Temperature Grades
Packages (by pin count)
PLCC
PQFP
VQFP
TQFP
PBGA
FBGA
A54SX08
8,000
12,000
768
512
256
130
3
Yes
–
3.7 ns
0.8 ns
Std, –1, –2, –3
C, I, M
84
208
100
144, 176
–
144
A54SX16
16,000
24,000
1,452
924
528
175
3
Yes
–
3.9 ns
0.5 ns
Std, –1, –2, –3
C, I, M
–
208
100
176
–
–
A54SX16P
16,000
24,000
1,452
924
528
175
3
Yes
Yes
4.4 ns
0.5 ns
Std, –1, –2, –3
C, I, M
–
208
100
144, 176
–
–
A54SX32
32,000
48,000
2,880
1,800
1,080
249
3
Yes
–
4.6 ns
0.1 ns
Std, –1, –2, –3
C, I, M
–
208
–
144, 176
313, 329
–
June 2006
© 2006 Actel Corporation
i
See the Actel website for the latest version of the datasheet.
SX Family FPGAs
Ordering Information
A54SX16
–
P
2
PQ
G
208
Application (Temperature Range)
Blank = Commercial (0 to +70˚C)
I = Industrial (–40 to +85˚C)
M = Military (–55 to +125˚C)
PP = Pre-production
Package Lead Count
Lead-Free Packaging
Blank = Standard Packaging
G = RoHS Compliant Packaging
Package Type
BG = Ball Grid Array
PL = Plastic Leaded Chip Carrier
PQ = Plastic Quad Flat Pack
TQ = Thin (1.4 mm) Quad Flat Pack
VQ = Very Thin (1.0 mm) Quad Flat Pack
FG = Fine Pitch Ball Grid Array (1.0 mm)
Speed Grade
Blank = Standard Speed
–1 = Approximately 15% Faster than Standard
–2 = Approximately 25% Faster than Standard
–3 = Approximately 35% Faster than Standard
Blank = Not PCI Compliant
P = PCI Compliant
Part Number
A54SX08 = 12,000 System Gates
A54SX16 = 24,000 System Gates
A54SX16P = 24,000 System Gates
A54SX32 = 48,000 System Gates
Plastic Device Resources
User I/Os (including clock buffers)
Device
A54SX08
A54SX16
A54SX16P
A54SX32
PLCC
84-Pin
69
–
–
–
VQFP
100-Pin
81
81
81
–
PQFP
208-Pin
130
175
175
174
TQFP
144-Pin
113
–
113
113
TQFP
176-Pin
128
147
147
147
PBGA
313-Pin
–
–
–
249
PBGA
329-Pin
–
–
–
249
FBGA
144-Pin
111
–
–
–
Note:
Package Definitions (Consult your local Actel sales representative for product availability):
PLCC = Plastic Leaded Chip Carrier
PQFP = Plastic Quad Flat Pack
TQFP = Thin Quad Flat Pack
VQFP = Very Thin Quad Flat Pack
PBGA = Plastic Ball Grid Array
FBGA = Fine Pitch (1.0 mm) Ball Grid Array
ii
v3.2
SX Family FPGAs
Table of Contents
SX Family FPGAs
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
SX Family Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
3.3 V / 5 V Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
PCI Compliance for the SX Family . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9
A54SX16P AC Specifications for (PCI Operation) . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10
A54SX16P DC Specifications (3.3 V PCI Operation) . . . . . . . . . . . . . . . . . . . . . . . . 1-12
A54SX16P AC Specifications (3.3 V PCI Operation) . . . . . . . . . . . . . . . . . . . . . . . . 1-13
Power-Up Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15
Power-Down Sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-15
Evaluating Power in SX Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-16
SX Timing Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-21
Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-23
Package Pin Assignments
84-Pin PLCC
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
208-Pin PQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3
144-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7
176-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
100-Pin VQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14
313-Pin PBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
329-Pin PBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19
144-Pin FBGA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23
Datasheet Information
List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
Datasheet Categories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
International Traffic in Arms Regulations (ITAR) and Export Administration
Regulations (EAR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
v3.2
iii
SX Family FPGAs
SX Family FPGAs
General Description
The Actel SX family of FPGAs features a sea-of-modules
architecture that delivers device performance and
integration levels not currently achieved by any other
FPGA architecture. SX devices greatly simplify design
time, enable dramatic reductions in design costs and
power consumption, and further decrease time to
market for performance-intensive applications.
The Actel SX architecture features two types of logic
modules, the combinatorial cell (C-cell) and the register
cell (R-cell), each optimized for fast and efficient
mapping of synthesized logic functions. The routing and
interconnect resources are in the metal layers above the
logic modules, providing optimal use of silicon. This
enables the entire floor of the device to be spanned with
an uninterrupted grid of fine-grained, synthesis-friendly
logic modules (or “sea-of-modules”), which reduces the
distance signals have to travel between logic modules. To
minimize signal propagation delay, SX devices employ
both local and general routing resources. The high-speed
local routing resources (DirectConnect and FastConnect)
enable very fast local signal propagation that is optimal
for fast counters, state machines, and datapath logic.
The general system of segmented routing tracks allows
any logic module in the array to be connected to any
other logic or I/O module. Within this system,
propagation delay is minimized by limiting the number
of antifuse interconnect elements to five (90 percent of
connections typically use only three antifuses). The
unique local and general routing structure featured in
SX devices gives fast and predictable performance,
allows 100 percent pin-locking with full logic utilization,
enables concurrent PCB development, reduces design
time, and allows designers to achieve performance goals
with minimum effort.
Further complementing SX’s flexible routing structure is
a hardwired, constantly loaded clock network that has
been tuned to provide fast clock propagation with
minimal clock skew. Additionally, the high performance
of the internal logic has eliminated the need to embed
latches or flip-flops in the I/O cells to achieve fast clock-
to-out or fast input setup times. SX devices have easy to
use I/O cells that do not require HDL instantiation,
facilitating design reuse and reducing design and
verification time.
SX Family Architecture
The SX family architecture was designed to satisfy next-
generation performance and integration requirements
for production-volume designs in a broad range of
applications.
Programmable Interconnect Element
The SX family provides efficient use of silicon by locating
the routing interconnect resources between the Metal 2
(M2) and Metal 3 (M3) layers (Figure
1-1 on page 1-2).
This completely eliminates the channels of routing and
interconnect resources between logic modules (as
implemented on SRAM FPGAs and previous generations
of antifuse FPGAs), and enables the entire floor of the
device to be spanned with an uninterrupted grid of logic
modules.
Interconnection between these logic modules is achieved
using The Actel patented metal-to-metal programmable
antifuse interconnect elements, which are embedded
between the M2 and M3 layers. The antifuses are
normally open circuit and, when programmed, form a
permanent low-impedance connection.
The extremely small size of these interconnect elements
gives the SX family abundant routing resources and
provides excellent protection against design pirating.
Reverse engineering is virtually impossible because it is
extremely difficult to distinguish between programmed
and unprogrammed antifuses, and there is no
configuration bitstream to intercept.
Additionally, the interconnect elements (i.e., the
antifuses and metal tracks) have lower capacitance and
lower resistance than any other device of similar
capacity, leading to the fastest signal propagation in the
industry.
Logic Module Design
The SX family architecture is described as a “sea-of-
modules” architecture because the entire floor of the
device is covered with a grid of logic modules with
virtually no chip area lost to interconnect elements or
routing. The Actel SX family provides two types of logic
modules, the register cell (R-cell) and the combinatorial
cell (C-cell).
v3.2
1-1
