A63L9336 Series
512K X 36 Bit Synchronous High Speed SRAM
with Burst Counter and Pipelined Data Output
Preliminary
Document Title
512K X 36 Bit Synchronous High Speed SRAM with Burst Counter and Pipelined
Data Output
Revision History
Rev. No.
0.0
History
Initial issue
Issue Date
March 26, 2007
Remark
Preliminary
PRELIMINARY
(March, 2007, Version 0.0)
AMIC Technology, Corp.
A63L9336 Series
512K X 36 Bit Synchronous High Speed SRAM
with Burst Counter and Pipelined Data Output
Preliminary
Features
Fast access times: 2.6/2.8/3.2/3.5/3.8/4.2 ns
(250/227/200/166/150/133 MH
Z
)
Single +3.3V+5% or +3.3V-5% power supply
Synchronous burst function
Individual Byte Write control and Global Write
Registered output for pipelined applications
Three separate chip enables allow wide range of
options for CE control, address pipelining
Selectable BURST mode
SLEEP mode (ZZ pin) provided
Available in 100-pin LQFP package
Industrial operating temperature range: -25°C to +85°C
for -I series
All Pb-free (lead-free) product are RoHS compliant
General Description
The A63L9336 is a high-speed SRAM containing 18M bits
of bit synchronous memory, organized as 512K words by
36 bits.
The A63L9336 combines advanced synchronous
peripheral circuitry, 2-bit burst control, input registers,
output registers and a 512KX36 SRAM core to provide a
wide range of data RAM applications.
The positive edge triggered single clock input (CLK)
controls all synchronous inputs passing through the
registers. Synchronous inputs include all addresses (A0 -
A18), all data inputs (I/O
1
- I/O
36
), active LOW chip enable
(
CE ), two additional chip enables (CE2, CE2 ), burst
control inputs (
ADSC , ADSP , ADV ), byte write enables
( BWE , BW1 , BW2 , BW3 , BW4 ) and Global Write
( GW ). Asynchronous inputs include output enable ( OE ),
clock (CLK), BURST mode (MODE) and SLEEP mode
(ZZ).
Burst operations can be initiated with either the address
status processor ( ADSP ) or address status controller
( ADSC ) input pin. Subsequent burst sequence burst
addresses can be internally generated by the A63L9336
and controlled by the burst advance ( ADV ) pin. Write
cycles are internally self-timed and synchronous with the
rising edge of the clock (CLK).
This feature simplifies the write interface. Individual Byte
enables allow individual bytes to be written. BW1 controls
I/O
1
- I/O
9
, BW2 controls I/O
10
- I/O
18
, BW3 controls
I/O
19
- I/O
27
, and BW4 controls I/O
28
- I/O
36
, all on the
condition that BWE is LOW. GW LOW causes all bytes
to be written.
PRELIMINARY
(March, 2007, Version 0.0)
1
AMIC Technology, Corp.
A63L9336 Series
Pin Configuration
ADSC
GND
VCC
ADSP
BWE
BW4
BW3
BW2
BW1
CLK
CE2
A6
A7
ADV
CE2
GW
OE
CE
A8
82
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
I/O
19
I/O
20
I/O
21
VCCQ
GNDQ
I/O
22
I/O
23
I/O
24
I/O
25
GNDQ
VCCQ
I/O
26
I/O
27
NC
VCC
NC
GND
I/O
28
I/O
29
VCCQ
GNDQ
I/O
30
I/O
31
I/O
32
I/O
33
GNDQ
VCCQ
I/O
34
I/O
35
I/O
36
100
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
A9
I/O
18
I/O
17
I/O
16
VCCQ
GNDQ
I/O
15
I/O
14
I/O
13
I/O
12
GNDQ
VCCQ
I/O
11
I/O
10
GND
NC
VCC
ZZ
I/O
8
I/O
7
VCCQ
GNDQ
I/O
6
I/O
5
I/O
4
I/O
3
GNDQ
VCCQ
I/O
2
I/O
1
I/O
9
A63L9336E
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
GND
VCC
NC
A18
A17
A5
A4
A3
A2
A1
A0
A10
A11
A12
A13
A14
A15
MODE
PRELIMINARY
(March, 2007, Version 0.0)
2
A16
NC
AMIC Technology, Corp.
A63L9336 Series
Block Diagram
ZZ
MODE
MODE
LOGIC
ADV
CLK
CLK
LOGIC
ADSC
ADSP
BURST
LOGIC
ADDRESS
COUNTER
CLR
A0-A18
ADDRESS
REGISTERS
19
8
BYTE1
WRITE
DRIVER
8
GW
BWE
BW1
BW2
BW3
BW4
BYTE
WRITE
ENABLE
LOGIC
8
BYTE2
WRITE
DRIVER
BYTE3
WRITE
DRIVER
BYTE4
WRITE
DRIVER
9
9
512KX9X4
36
MEMORY
OUTPUT
REGISTERS
ARRAY
9
8
9
36
4
DATA-IN
REGISTERS
4
CE
CE2
CE2
CHIP
ENABLE
LOGIC
PIPELINED
ENABLE
LOGIC
OE
I/O
1
- I/O
36
OUTPUT
ENABLE
LOGIC
PRELIMINARY
(March, 2007, Version 0.0)
3
AMIC Technology, Corp.
A63L9336 Series
Pin Description
Pin No.
Symbol
Description
32 – 37, 42 - 50, 81, 82,
99, 100
89
87, 93 - 96
88
86
92, 97, 98
83
84
85
31
A0 - A18
Address Inputs
CLK
BWE , BW1 - BW4
GW
OE
CE2 ,CE2, CE
ADV
ADSP
ADSC
MODE
Clock
Byte Write Enables
Global Write
Output Enable
Chip Enables
Burst Address Advance
Processor Address Status
Controller Address Status
Burst Mode: HIGH or NC (Interleaved burst)
LOW (Linear burst)
Asynchronous Power-Down (Snooze): HIGH (Sleep)
LOW or NC (Wake up)
Data Inputs/Outputs
64
ZZ
1,2, 3, 6 - 9, 12, 13, 18,
19, 22 - 25, 28, 29,
30,51,52, 53,
56 - 59, 62, 63, 68, 69, 72
- 75, 78, 79,80
15, 41, 65, 91
17, 40, 67, 90
4, 11, 20, 27,
54, 61, 70, 77
5, 10, 21, 26,
55, 60, 71, 76
I/O
1
- I/O
36
VCC
GND
VCCQ
Power Supply
Ground
Isolated Output Buffer Supply
GNDQ
Isolated Output Buffer Ground
PRELIMINARY
(March, 2007, Version 0.0)
4
AMIC Technology, Corp.
