A63P06361
Preliminary
Document Title
1M X 36 Bit Synchronous High Speed SRAM with Burst Counter and Flow-through
Data Output
Revision History
Rev. No.
0.0
1M X 36 Bit Synchronous High Speed SRAM with
Burst Counter and Flow-through Data Output
History
Initial issue
Issue Date
August 25, 2005
Remark
Preliminary
PRELIMINARY
(August, 2005, Version 0.0)
AMIC Technology, Corp.
A63P06361
Preliminary
Features
Fast access times: 6.5/7.5/8.0 ns(153/133/117 MHz)
Single 2.5V±5% power supply
Synchronous burst function
Individual Byte Write control and Global Write
Three separate chip enables allow wide range of
options for CE control, address pipelining
Selectable BURST mode
SLEEP mode (ZZ pin) provided
Available in 100-pin LQFP package
Industrial operating temperature range: -45°C to
+125°C for -I series
1M X 36 Bit Synchronous High Speed SRAM with
Burst Counter and Flow-through Data Output
General Description
The A63P06361 is a high-speed SRAM containing 36M
bits of bit synchronous memory, organized as 1024K
words by 36 bits.
The A63P06361 combines advanced synchronous
peripheral circuitry, 2-bit burst control, input registers,
output buffer and a 1M X 36 SRAM core to provide a wide
range of data RAM applications.
The positive edge triggered single clock input (CLK)
controls all synchronous inputs passing through the
registers. Synchronous inputs include all addresses (A0 -
A19), all data inputs (I/O
1
- I/O
36
), active LOW chip
enable (
CE ), two additional chip enables (CE2, CE2 ),
burst control inputs ( ADSC , ADSP , ADV ), byte write
enables ( BWE , BW1 , BW2 , BW3 , BW4 ) and Global
Write ( GW ). Asynchronous inputs include output enable
( OE ), clock (CLK), BURST mode (MODE) and SLEEP
mode (ZZ).
Burst operations can be initiated with either the address
status processor ( ADSP ) or address status controller
( ADSC ) input pin. Subsequent burst sequence burst
addresses can be internally generated by the A63P06361
and controlled by the burst advance ( ADV ) pin. Write
cycles are internally self-timed and synchronous with the
rising edge of the clock (CLK).
This feature simplifies the write interface. Individual Byte
enables allow individual bytes to be written. BW1 controls
I/O
1
- I/O
9
, BW2 controls I/O
10
- I/O
18
, BW3 controls
I/O
19
- I/O
27
, and BW4 controls I/O
28
- I/O
36
, all on the
condition that BWE is LOW. GW LOW causes all bytes
to be written.
PRELIMINARY
(August, 2005, Version 0.0)
1
AMIC Technology, Corp.
A63P06361
Pin Configuration
ADSC
BW4
BW3
BW2
BW1
BWE
GND
VCC
ADSP
CE2
CE2
CLK
GW
A6
A7
OE
CE
ADV
A8
82
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
I/O
19
I/O
20
I/O
21
VCCQ
GNDQ
I/O
22
I/O
23
I/O
24
I/O
25
GNDQ
VCCQ
I/O
26
I/O
27
100
81
A9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
80
79
78
77
76
75
74
73
72
71
70
69
68
67
I/O
18
I/O
17
I/O
16
VCCQ
GNDQ
I/O
15
I/O
14
I/O
13
I/O
12
GNDQ
VCCQ
I/O
11
I/O
10
GND
NC
VCC
ZZ
I/O
8
I/O
7
VCCQ
GNDQ
I/O
6
I/O
5
I/O
4
I/O
3
GNDQ
VCCQ
I/O
2
I/O
1
NC
VCC
NC
GND
I/O
28
I/O
29
VCCQ
GNDQ
I/O
30
I/O
31
I/O
32
I/O
33
GNDQ
VCCQ
I/O
34
I/O
35
A63P06361E
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
I/O
36
I/O
9
A5
A4
A3
A2
A1
MODE
A0
GND
VCC
NC
A19
A18
A10
A11
A12
A13
A14
A15
A16
PRELIMINARY
(August, 2005, Version 0.0)
2
A17
AMIC Technology, Corp.
A63P06361
Block Diagram
ZZ
MODE
MODE
LOGIC
ADV
CLK
CLK
LOGIC
ADSC
ADSP
BURST
LOGIC
ADDRESS
COUNTER
CLR
A0-A19
ADDRESS
REGISTERS
20
9
BYTE1
WRITE
DRIVER
BYTE2
WRITE
DRIVER
BYTE3
WRITE
DRIVER
BYTE4
WRITE
DRIVER
9
9
GW
BWE
BW1
BW2
BW3
BW4
9
1MX9X4
MEMORY
36
BYTE
WRITE
ENABLE
LOGIC
OUTPUT
BUFFER
9
9
ARRAY
9
9
36
4
DATA-IN
REGISTERS
4
CE
CE2
CE2
OE
I/O
1
- I/O
36
CHIP
ENABLE
LOGIC
OUTPUT
ENABLE
LOGIC
PRELIMINARY
(August, 2005, Version 0.0)
3
AMIC Technology, Corp.
A63P06361
Pin Description
Pin No.
Symbol
Description
32 – 37,39, 42 - 50, 81,
82, 99, 100
89
87, 93 - 96
88
86
92, 97, 98
83
84
85
31
A0 - A19
Address Inputs
CLK
BWE , BW1 - BW4
GW
OE
CE2 ,CE2, CE
ADV
ADSP
ADSC
MODE
Clock
Byte Write Enables
Global Write
Output Enable
Chip Enables
Burst Address Advance
Processor Address Status
Controller Address Status
Burst Mode: HIGH or NC (Interleaved burst)
LOW (Linear burst)
Asynchronous Power-Down (Snooze): HIGH (Sleep)
LOW or NC (Wake up)
Data Inputs/Outputs
64
ZZ
1,2, 3, 6 - 9, 12, 13, 18,
19, 22 - 25, 28, 29,30,51,
52, 53,
56 - 59, 62, 63, 68, 69, 72
- 75, 78, 79,80
1, 14, 16, 30, 38, 39, 42,
43, 51, 66, 80
15, 41, 65, 91
17, 40, 67, 90
4, 11, 20, 27,
54, 61, 70, 77
5, 10, 21, 26,
55, 60, 71, 76
I/O
1
- I/O
36
NC
No Connection
VCC
GND
VCCQ
Power Supply
Ground
Isolated Output Buffer Supply
GNDQ
Isolated Output Buffer Ground
PRELIMINARY
(August, 2005, Version 0.0)
4
AMIC Technology, Corp.
