A6850
Dual Channel Switch Interface IC
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Features and Benefits
4.75 to 26.5 V operation
Low V
IN
-to-V
OUT
voltage drop
1
/ current sense feedback
10
Survive short-to-battery and short-to-ground faults
Survive 40 V load dump
>4 kV ESD rating on the output pins, >2 kV on all other pins
Output current limiting
Low operating and Sleep mode currents
Integrates with Allegro A114x and A118x Hall effect
two-wire sensors
Description
The Allegro
®
A6850 is designed to interface between a
microprocessor and a pair of 2-wire Hall effect sensors.
The A6850 uses protected high-side low resistance DMOS
MOSFETs to switch the supply voltage to the two Hall effect
devices. Each switch can be controlled independently via
individual ENABLE pins and both switches are protected
with current-limiting circuitry. The output switches are rated
to operate to 26.5 V and will source at least 25 mA per channel
before current limiting.
Typical two-wire Hall sensor applications require the user
to measure the supply current to determine whether the Hall
sensor is switched on (magnetic field present) or switched off
(no magnetic field present). This is usually accomplished by
using an external series shunt resistor and protection circuits
for the microprocessor. In many systems, the sensed voltage is
used as the input to a microprocessor analog-to-digital (A-to-D)
input. This provides the system with an indication of the status
of the two-wire switch as well as provides the capability for
diagnostic information if there is an open or shorted sensor.
Package: 8 pin SOIC (suffix L)
Approximate Scale 1:1
Continued on the next page…
Functional Block Diagram
VIN
ENABLE1
Control
Block
ENABLE2
SENSE1
1
/
10
×
I
OUTPUT1
Fault
Detection
OUTPUT1
SENSE2
1
/
10
×
I
OUTPUT2
Fault
Detection
OUTPUT2
GROUND
6850-DS
A6850
Description (continued)
The A6850 eliminates the need for the external series shunt resistor
in Hall sensor applications by incorporating an integrated current
mirror which reports the Hall sensor supply current as a
1
/
10
value
on the SENSE1 or SENSE2 output pin. A low current Sleep mode
Dual Channel Switch Interface IC
is available (<15 µA) by driving both ENABLE pins low. Also, the
A6850 can be used to interface to mechanical switches.
The A6850 is supplied in an 8-pin Pb (lead) free SOIC package,
with 100% matte tin leadframe plating.
Selection Guide
A6850KLTR-T
A6850KL-T
Part Number
Packing
13-in. reel, 3000 pieces/reel
Tube, 98 pieces/tube
Absolute Maximum Ratings
Characteristic
Supply Voltage
Output Voltage
SENSEx Voltage Range
ENABLEx Voltage Range
Operating Ambient Temperature
Maximum Junction Temperature
Storage Temperature
ESD Rating - Human Body Model
ESD Rating - Charged Device Model
Symbol
V
IN
V
OUTPUTx
V
SENSEx
V
ENABLEx
T
A
T
J
(max)
T
stg
HBM
CDM
AEC-Q100-00; OUTPUT1 and OUTPUT
AEC-Q100-00; all other pins
AEC-Q100-011; all pins
Range K
Notes
Rating
40
–0.3 to 40
–0.3 to 7
–0.3 to 7
–40 to 15
150
–55 to 150
4.5
.5
1050
Units
V
V
V
V
ºC
ºC
ºC
kV
kV
V
Pin-out Diagram
Terminal List Table
Name
ENABLE1
Number
1
3
4
5
6
7
8
Description
Digital input pulled to ground
Sensed current output
Digital input pulled to ground
Sensed current output
Chip power supply voltage
Switchable voltage supply to sensor
Ground reference
Switchable voltage supply to sensor
ENABLE1
1
Control
Switch
8
OUTPUT1
SENSE1
ENABLE
SENSE
VIN
OUTPUT
GROUND
OUTPUT1
SENSE1
2
7
GROUND
ENABLE2
3
Switch
6
OUTPUT2
SENSE2
4
5
VIN
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
A6850
Dual Channel Switch Interface IC
ELECTRICAL CHARACTERISTICS at T
J
= -40 to +150°C (unless noted otherwise)
Characteristics
Symbol
Test Conditions
Supply Input Voltage Range
V
IN
Operating mode, I
OUTPUTx
= 0 mA
Sleep mode:
Supply Input Quiescent Current
I
INQ
ENABLE1 and ENABLE low
V
OUTPUT1
= V
OUTPUT
= 0 V
1
Power-Up Time
t
ON
OUTPUTx Source Resistance
R
DS(on)
I
OUTPUTx
= 0 mA
OUTPUTx Leakage Current
I
OUTPUTQ
V
OUTPUTx
= 0 V; disabled
I
SENSEx
= (I
OUTPUTx
/ 10) +
I
SENSE(ofs)
I
SENSE(ofs)
, I
OUTPUT
= mA to 0 mA
SENSEx Output Current Offset
I
SENSEQ
V
SENSEx
= 0 V; disabled
V
IN
> 7 V
SENSEx Voltage
3
V
SENSEx
V
IN
< 7 V
V
ENABLEH
ENABLEx Input Voltage Range
V
ENABLEL
ENABLEx Input Hysteresis
V
ENABLEhys
At least one output enabled
ENABLEx = .0 V
ENABLEx Current
I
ENABLE
ENABLEx = 0.4 V
OUTPUT Current Limit
I
OUTPUTM
Reverse bias blocking: V
IN
= 4.75 V,
OUTPUT Reverse Bias Current
I
OUTPUT(rvrs)
V
OUTPUT
= 6.5 V
Overvoltage Protection Threshold
V
OVP
Rising V
IN
Overvoltage Protection Hysteresis
V
OVPhys
Thermal Shutdown Threshold
T
TSD
Temperature Increasing
Thermal Shutdown Hysteresis
T
TSDhys
1
Delay
For
Min.
4.75
–
–
–
–
–
–100
–
0
0
.0
–
150
–
–
5.0
–
7.0
–
–
–
Typ.
–
–
–
–
–
–
–
–
–
–
–
–
–
40
8.0
35.0
500
–
.0
175
15
Max.
6.5
5.0
15
0
35
0
100
10
6
V
IN
– 1
–
0.4
350
100
0
45.0
750
33.0
–
–
–
Units
V
mA
µA
µs
Ω
µA
µA
µA
V
V
V
V
mV
µA
µA
mA
µA
V
V
°C
°C
from end of Sleep mode to outputs enabled.
input and output current specifications, negative current is defined as coming out of (sourced from) the specified device pin.
3
User to ensure that V
SENSEx
remains within the specified range. If V
SENSEx
exceeds the maximum value, the device is self-protected by an
internal clamp, but not all parameters perform as specified.
THERMAL CHARACTERISTICS may require derating at maximum conditions, see application information
Characteristic
Package Thermal Resistance
Symbol
R
θJA
Test Conditions*
4-layer PCB based on JEDEC standard
1-layer PCB with copper limited to solder pads
Value
80
140
Units
ºC/W
ºC/W
*Additional thermal data available on the Allegro Web site.
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
3
A6850
Dual Channel Switch Interface IC
Functional Description
Thermal Shutdown (TSD)
The A6850 protects itself from excessive heat damage by
disabling both outputs when the junction temperature, T
J
,
rises above the TSD threshold (T
TSD
). The outputs will
remain off until the junction temperature falls below the
T
TSD
level minus the TSD hysteresis, T
TSDhys
.
T
J
can be estimated by calculating the power dissipation (P
D
)
of the A6850. To calculate P
D
:
P
D
=
V
IN
I
INQ
–
V
OUTPUT1
I
OUTPUT1
–
V
OUTPUT2
I
OUTPUT2
–
V
SENSE1
I
SENSE1
–
V
SENSE2
I
SENSE2
.
P
D
=
V
IN
I
INQ
+ (V
IN
–
V
OUTPUT1
)
I
OUTPUT1
+ (V
IN
–
V
OUTPUT2
)
I
OUTPUT2
+ (V
IN
–
V
SENSE1 )
I
SENSE1
+ (V
IN
–
V
SENSE2 )
I
SENSE2
.
The temperature rise of the A6850 can be calculated by
multiplying P
D
and the thermal resistance from junction to
ambient, R
θJA
. The formula for temperature rise,
ΔT,
is:
ΔT
=
P
D
×
R
θJA
.
(3)
The R
θJA
for an 8-pin SOIC (Allegro L package) on a one-
layer board with minimum copper area is 140
°
C / W. (More
thermal data is available on the Allegro MicroSystems Web
site.)
The total junction temperature can be calculated by:
T
J
=
T
A
+
ΔT
,
where T
A
is the ambient air temperature.
(4)
(2)
(1)
Example:
Calculating the power dissipation and temperature
rise, given:
T
A
= 25
°
C,
V
IN
= 5 V,
I
INQ
= 5 mA,
I
OUTPUT1
= I
OUTPUT2
= 15 mA,
V
Dropx
= V
IN
– V
OUTPUTx
=
0.7 V,
I
SENSEx
= I
OUTPUTx
/10 = 1.5 mA, and
R
SENSE1
= R
SENSE2
= 2 kΩ.
Then:
P
D
= 5 V × 5 mA
+ 0.7 V×15 mA+[5 V – (1.5 mA×2 kΩ)]×1.5
mA
+ 0.7 V×15 mA+[5 V – (1.5 mA×2 kΩ)]×1.5
mA
= 52 mW .
ΔT = 52 mW × 140
°
C / W = 7.3
°
C .
Substituting in equation 4:
T
J
= 25
°
C + 7.3
°
C = 32.3
°
C .
Substituting in equation 3:
Output Current Limit
The A6850 limits the output current to a maximum current
of I
OUTPUTM
. The output current will remain at the current
limit until the output load is reduced or the A6850 goes into
thermal shutdown.
The high output current limit allows the bypass capacitor,
C
BYP
, on the Hall sensor to charge up quickly. This allows
a high slew rate on the VCC pin of the Hall sensor, ensur-
ing that the sensor Power-On State will be correct. See the
Applications Information section for schematic diagrams and
power calculations.
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
4
A6850
Dual Channel Switch Interface IC
Output Faults
The A6850 withstands short-to-ground or short-to-battery of
the OUTPUTx pins. In the case of short-to-ground, current is
held to the current limit (I
OUTPUTM
).
If V
OUTPUTx
> (V
IN
+ 0.7 V) during short-to-battery, the
A6850 monitors V
OUTPUTx
and disables the outputs. Because
the protection circuitry requires a finite amount of time to
disable the outputs, a bypass capacitor of 1 µF is necessary
on VIN. Although OUTPUTx sinks current into the A6850 in
this state, the current is bled to ground and does not charge-
up capacitors tied to VIN.
limits on the sense pin (see Electrical Characteristics table).
Sleep Mode
Low-leakage or sleep modes are required in automotive
applications to minimize battery drain when the vehicle is
parked. The A6850 enters sleep mode when both ENABLE
pins are low. In sleep mode, the internal regulators and all
other internal circuitry are disabled.
When enabling an output, the part must first come out of
sleep mode. Consequently, the wake-up time amounts to
a propagation delay before the outputs turn on. Also, the
ENABLE pins do not switch with hysteresis until the regula-
tors stabilize.
After the internal regulators stabilize, internal circuitry is
enabled and the outputs turn on, as shown in figure 1. As
long as one ENABLE pin is held high, the A6850 operates
with hysteresis.
Overvoltage Protection
The A6850 has built-in overvoltage protection against a load
dump on the supply bus. In the case of a load dump, or when
V
IN
is connected to the battery supply bus and V
IN
rises
above the overvoltage threshold, V
OVP
, the A6850 will shut
off the outputs.
SENSE Pin Outputs
The A6850 divides the OUTPUTx pin current by 10 and
mirrors it onto the corresponding SENSEx pin. Putting sense
resistors, RSENSE , from these pins to ground will create
a voltage that can be read by an ADC (analog-to-digital
converter). The value of R
SENSE
should be chosen so that
the voltage drop across the sense resistor (V
RSENSE
) does not
exceed the maximum voltage rating of the ADC. For further
protection of the ADC, an external clamping circuit, such
as a Zener diode, can be used to clamp any transient current
spikes that may occur on the output that would be translated
onto the SENSE pins.
The sense current is one tenth of the output current, plus an
offset current. This offset current is consistent across the
whole range of the output current. The sense current can be
calculated by the following formula:
I
SENSEx
= (I
OUTPUTx
/ 10) +
I
SENSE(ofs)
.
(5)
The sense resistor must also be chosen to meet the voltage
ENABLE
V
ENABLEL
> t
ON
RegOk
V
REG
OUTPUT
Figure 1. Activation Timing Diagram. Exiting Sleep mode
via ENABLE signal to output waveform.
Allegro MicroSystems, Inc.
115 Northeast Cutoff, Box 15036
Worcester, Massachusetts 01615-0036 (508) 853-5000
www.allegromicro.com
5
