EVALUATION BOARD DATASHEET
EV-175
AAT4712 EVAL: Power Path with Input Current Limit and Capacitor Charger
Introduction
The AAT4712 is an integrated P-channel MOSFET load switch with adjustable current limits, integrated discharge path,
over temperature protection, a power loop and a super capacitor charger. The input current limit control is combined
with an over-temperature thermal limit and power loop circuit to provide a comprehensive system to protect the load
switch and its supply from load conditions exceeding the supply specifications.
A brief “Getting Started” section is included to help the user to begin operating the evaluation board. The AAT4712
evaluation board is shown in Figure 1; Figures 2 and 8 depict the board schematic and layout. For additional informa-
tion, please consult the AAT4712 product datasheet.
Board Picture
(a) Top Side
(b) Bottom Side
Figure 1: AAT4712 Evaluation Board Picture.
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EVALUATION BOARD DATASHEET
EV-175
AAT4712 EVAL: Power Path with Input Current Limit and Capacitor Charger
Schematic
VCC
D1
LED
R1
100K
RDY
R
SET
1.24M
U1
AAT4712
1
2
3
4
SYS
5
6
7
8
C2
10μF
RDY
ISET
NC
SYS
SYS
SYS
SYS
SYS
POK
GND
ADJ
VCC
VCC
OUT
OUT
OUT
16
15
14
13
12
11
10
9
C3
22μF
Super Cap
RB2
C1
10μF
R
ADJ
18.2k
VCC
VCC
D2
LED
R2
100k
POK
GND
OUT
RB1
Figure 2: AAT4712 Evaluation Board Schematic.
Getting Started
Connect a DC power supply and a super capacitor or ultra capacitor to the AAT4712 evaluation board as shown in
Figure 3. Set the DC power supply to 5V and the load to 0A. After power on, a current up to the current limit (2A
set by R
SET
= 1.24M) charging the super capacitor can be observed by either current meter in the power supply or
current probe of an oscilloscope. Figure 4 shows the start-up waveform of charging the super capacitor with soft-
start at 5V V
CC
. The operating voltage may vary from 2.5V to 5.5V.
2. After the power is on and the super capacitor is fully charged, the integrated discharge path management can be
observed by decreasing the V
CC
with system load added. The AAT4712 integrates discharge path for SYS (to system
load) from the VCC input and OUT input (connect to super capacitor). After the power is on and the super capaci-
tor is fully charged, the super capacitor is used as a backup power to support the system load for a short time when
the input voltage drops below the power good detect (POK) threshold and the OUT pin voltage is greater than the
V
UVLO_OUT
and SYS voltage by turning on the OUT to SYS switch discharge path and turning off the path of V
CC
to
SYS. The OUT to SYS switch remains continuously on until the OUT pin voltage falls below V
UVLO_OUT
.
1.
2
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EV-175.2010.07.1.0
EVALUATION BOARD DATASHEET
EV-175
AAT4712 EVAL: Power Path with Input Current Limit and Capacitor Charger
Electronic LOAD
0 to 2A
0.5F 75mΩ (TDK
EDLC272020 -501-2F-50) is
adopted as SuperCap for the
measurement of the file . The
balance resistors are 11kΩ.
I
SYS
Power Supply
2.5V to 5.5V
I
OUT
I
CC
Figure 3: AAT4712 Evaluation Board Demonstration Connection.
(a) Zoom in
(b) Zoom out
Figure 4: AAT4712 Start-up without System Load.
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EVALUATION BOARD DATASHEET
EV-175
AAT4712 EVAL: Power Path with Input Current Limit and Capacitor Charger
Figure 5 shows the dynamic process of the power path switching with V
POK_TH
= 4.5V, 0.5F super capacitor with 75mΩ
ESR, V
CC
drops from 5V to 4V with 1A system load. D2 will be lighted when the OUT to SYS path is turned on and VCC
to the SYS path is turned off.
Figure 6 shows the waveform of the super capacitor supporting the system load as backup power when V
CC
is removed.
The supporting time can be calculated using the following formula:
T
SUPPORT
= (V
DROP
· I
OUT
· ESR
SUPERCAP
) ·
C
SUPERCAP
I
OUT
V
DROP
is the delta voltage when the super capacitor is active to support the system load and is equal to V
CC
minus
V
UVLO_OUT
.
For the condition as shown in Figure 6, the V
DROP
is 3V by V
CC
5V minus V
UVLO_OUT
2V. The supporting time can be calcu-
lated using the following equation. The calculation result is same as the measurement result.
T
SUPPORT
= (3V - 1A · 75mΩ) ·
0.5F
= 1.46 sec.
1A
Discharge path management by the AAT4712 can also be observed by observing the input current I
CC
, system load I
SYS
,
and super capacitor charge current I
OUT
. The input current is equal to the SYS current plus the OUT charging current as
shown in the formula below and if the SYS load current increases/decreases, the OUT charging current will automati-
cally decrease/increase accordingly via the device control loop.
I
CC
= I
SYS
+ I
OUT
Figure 7 shows the measurement waveform when powering on the AAT4712 with 1A system load. Make sure the super
capacitor is fully discharged before doing the measurement.
Figure 5: AAT4712 Operating Waveform When
V
CC
Drops from 5V to 4V with 1A System Load.
Figure 6: AAT4712 Backup Time when 5V V
CC
is
Removed with 1A System Load and 0.5F SuperCap.
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EV-175.2010.07.1.0
EVALUATION BOARD DATASHEET
EV-175
AAT4712 EVAL: Power Path with Input Current Limit and Capacitor Charger
Figure 7: AAT4712 Startup with 1A System Load.
Current Limit and POK Setting
The input current limit is programmed by by the R
SET
resistor from the I
SET
pin to ground in the range from 150mA to
2.4A. R
SET
can be calculated by:
R
SET
=
I
LIM
1.6
Table 1 lists some 1% standard metal film resistor values for current limit settings.
R
SET
(kΩ)
1500
1240
1000
931
750
620
560
499
432
374
316
249
187
93.1
Current Limit (A)
2.4
2
1.6
1.5
1.2
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.15
Table 1: Recommended Current Limit R
SET
Values.
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